197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))  macro
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);  in tegra_thermctl_get_temp()
1305 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);  in regs_show()
1315 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);  in regs_show()
1317 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);  in regs_show()
1319 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);  in regs_show()
1323 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);  in regs_show()
1325 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);  in regs_show()
1329 		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);  in regs_show()
1331 		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);  in regs_show()
1335 		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);  in regs_show()
1337 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);  in regs_show()
1339 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);  in regs_show()
1341 		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);  in regs_show()
1343 		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);  in regs_show()
1347 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);  in regs_show()
1349 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);  in regs_show()
1363 	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);  in regs_show()
1365 	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);  in regs_show()
1368 	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);  in regs_show()
1370 	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);  in regs_show()
1383 			state = REG_GET_MASK(r, mask);  in regs_show()
1389 			state = REG_GET_MASK(r, mask);  in regs_show()
1395 			state = REG_GET_MASK(r, mask);  in regs_show()
1399 			state = REG_GET_MASK(r, mask);  in regs_show()
1411 			state = REG_GET_MASK(r, mask);  in regs_show()
1423 			state = REG_GET_MASK(r, mask);  in regs_show()
1449 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);  in regs_show()
1452 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);  in regs_show()
1454 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);  in regs_show()
1465 	state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);  in regs_show()
1467 	state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);  in regs_show()
1469 	state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);  in regs_show()
1474 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1477 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);  in regs_show()
1479 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);  in regs_show()
1481 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1552 	if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))  in throt_get_cdev_cur_state()
1964 	r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);  in soctherm_throttle_program()