Lines Matching refs:tsd

139 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,  in tegra_sflash_readl()  argument
142 return readl(tsd->base + reg); in tegra_sflash_readl()
145 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd, in tegra_sflash_writel() argument
148 writel(val, tsd->base + reg); in tegra_sflash_writel()
151 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd) in tegra_sflash_clear_status() argument
154 tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS); in tegra_sflash_clear_status()
158 struct spi_device *spi, struct tegra_sflash_data *tsd, in tegra_sflash_calculate_curr_xfer_param() argument
161 unsigned remain_len = t->len - tsd->cur_pos; in tegra_sflash_calculate_curr_xfer_param()
164 tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8); in tegra_sflash_calculate_curr_xfer_param()
165 max_word = remain_len / tsd->bytes_per_word; in tegra_sflash_calculate_curr_xfer_param()
168 tsd->curr_xfer_words = max_word; in tegra_sflash_calculate_curr_xfer_param()
173 struct tegra_sflash_data *tsd, struct spi_transfer *t) in tegra_sflash_fill_tx_fifo_from_client_txbuf() argument
177 unsigned max_n_32bit = tsd->curr_xfer_words; in tegra_sflash_fill_tx_fifo_from_client_txbuf()
178 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos; in tegra_sflash_fill_tx_fifo_from_client_txbuf()
182 nbytes = max_n_32bit * tsd->bytes_per_word; in tegra_sflash_fill_tx_fifo_from_client_txbuf()
184 status = tegra_sflash_readl(tsd, SPI_STATUS); in tegra_sflash_fill_tx_fifo_from_client_txbuf()
189 for (i = 0; nbytes && (i < tsd->bytes_per_word); in tegra_sflash_fill_tx_fifo_from_client_txbuf()
192 tegra_sflash_writel(tsd, x, SPI_TX_FIFO); in tegra_sflash_fill_tx_fifo_from_client_txbuf()
196 status = tegra_sflash_readl(tsd, SPI_STATUS); in tegra_sflash_fill_tx_fifo_from_client_txbuf()
198 tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word; in tegra_sflash_fill_tx_fifo_from_client_txbuf()
203 struct tegra_sflash_data *tsd, struct spi_transfer *t) in tegra_sflash_read_rx_fifo_to_client_rxbuf() argument
207 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos; in tegra_sflash_read_rx_fifo_to_client_rxbuf()
209 status = tegra_sflash_readl(tsd, SPI_STATUS); in tegra_sflash_read_rx_fifo_to_client_rxbuf()
212 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO); in tegra_sflash_read_rx_fifo_to_client_rxbuf()
214 for (i = 0; (i < tsd->bytes_per_word); i++) in tegra_sflash_read_rx_fifo_to_client_rxbuf()
217 status = tegra_sflash_readl(tsd, SPI_STATUS); in tegra_sflash_read_rx_fifo_to_client_rxbuf()
219 tsd->cur_rx_pos += read_words * tsd->bytes_per_word; in tegra_sflash_read_rx_fifo_to_client_rxbuf()
224 struct tegra_sflash_data *tsd, struct spi_transfer *t) in tegra_sflash_start_cpu_based_transfer() argument
229 if (tsd->cur_direction & DATA_DIR_TX) in tegra_sflash_start_cpu_based_transfer()
232 if (tsd->cur_direction & DATA_DIR_RX) in tegra_sflash_start_cpu_based_transfer()
235 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); in tegra_sflash_start_cpu_based_transfer()
236 tsd->dma_control_reg = val; in tegra_sflash_start_cpu_based_transfer()
238 if (tsd->cur_direction & DATA_DIR_TX) in tegra_sflash_start_cpu_based_transfer()
239 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t); in tegra_sflash_start_cpu_based_transfer()
241 cur_words = tsd->curr_xfer_words; in tegra_sflash_start_cpu_based_transfer()
243 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); in tegra_sflash_start_cpu_based_transfer()
244 tsd->dma_control_reg = val; in tegra_sflash_start_cpu_based_transfer()
246 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); in tegra_sflash_start_cpu_based_transfer()
254 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); in tegra_sflash_start_transfer_one() local
259 if (speed != tsd->cur_speed) { in tegra_sflash_start_transfer_one()
260 clk_set_rate(tsd->clk, speed); in tegra_sflash_start_transfer_one()
261 tsd->cur_speed = speed; in tegra_sflash_start_transfer_one()
264 tsd->cur_spi = spi; in tegra_sflash_start_transfer_one()
265 tsd->cur_pos = 0; in tegra_sflash_start_transfer_one()
266 tsd->cur_rx_pos = 0; in tegra_sflash_start_transfer_one()
267 tsd->cur_tx_pos = 0; in tegra_sflash_start_transfer_one()
268 tsd->curr_xfer = t; in tegra_sflash_start_transfer_one()
269 tegra_sflash_calculate_curr_xfer_param(spi, tsd, t); in tegra_sflash_start_transfer_one()
271 command = tsd->def_command_reg; in tegra_sflash_start_transfer_one()
285 command = tsd->command_reg; in tegra_sflash_start_transfer_one()
291 tsd->cur_direction = 0; in tegra_sflash_start_transfer_one()
294 tsd->cur_direction |= DATA_DIR_RX; in tegra_sflash_start_transfer_one()
298 tsd->cur_direction |= DATA_DIR_TX; in tegra_sflash_start_transfer_one()
300 tegra_sflash_writel(tsd, command, SPI_COMMAND); in tegra_sflash_start_transfer_one()
301 tsd->command_reg = command; in tegra_sflash_start_transfer_one()
303 return tegra_sflash_start_cpu_based_transfer(tsd, t); in tegra_sflash_start_transfer_one()
311 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); in tegra_sflash_transfer_one_message() local
320 reinit_completion(&tsd->xfer_completion); in tegra_sflash_transfer_one_message()
324 dev_err(tsd->dev, in tegra_sflash_transfer_one_message()
329 ret = wait_for_completion_timeout(&tsd->xfer_completion, in tegra_sflash_transfer_one_message()
332 dev_err(tsd->dev, in tegra_sflash_transfer_one_message()
338 if (tsd->tx_status || tsd->rx_status) { in tegra_sflash_transfer_one_message()
339 dev_err(tsd->dev, "Error in Transfer\n"); in tegra_sflash_transfer_one_message()
346 tegra_sflash_writel(tsd, tsd->def_command_reg, in tegra_sflash_transfer_one_message()
353 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); in tegra_sflash_transfer_one_message()
359 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd) in handle_cpu_based_xfer() argument
361 struct spi_transfer *t = tsd->curr_xfer; in handle_cpu_based_xfer()
363 spin_lock(&tsd->lock); in handle_cpu_based_xfer()
364 if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) { in handle_cpu_based_xfer()
365 dev_err(tsd->dev, in handle_cpu_based_xfer()
366 "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg); in handle_cpu_based_xfer()
367 dev_err(tsd->dev, in handle_cpu_based_xfer()
368 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, in handle_cpu_based_xfer()
369 tsd->dma_control_reg); in handle_cpu_based_xfer()
370 reset_control_assert(tsd->rst); in handle_cpu_based_xfer()
372 reset_control_deassert(tsd->rst); in handle_cpu_based_xfer()
373 complete(&tsd->xfer_completion); in handle_cpu_based_xfer()
377 if (tsd->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
378 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t); in handle_cpu_based_xfer()
380 if (tsd->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
381 tsd->cur_pos = tsd->cur_tx_pos; in handle_cpu_based_xfer()
383 tsd->cur_pos = tsd->cur_rx_pos; in handle_cpu_based_xfer()
385 if (tsd->cur_pos == t->len) { in handle_cpu_based_xfer()
386 complete(&tsd->xfer_completion); in handle_cpu_based_xfer()
390 tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t); in handle_cpu_based_xfer()
391 tegra_sflash_start_cpu_based_transfer(tsd, t); in handle_cpu_based_xfer()
393 spin_unlock(&tsd->lock); in handle_cpu_based_xfer()
399 struct tegra_sflash_data *tsd = context_data; in tegra_sflash_isr() local
401 tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS); in tegra_sflash_isr()
402 if (tsd->cur_direction & DATA_DIR_TX) in tegra_sflash_isr()
403 tsd->tx_status = tsd->status_reg & SPI_TX_OVF; in tegra_sflash_isr()
405 if (tsd->cur_direction & DATA_DIR_RX) in tegra_sflash_isr()
406 tsd->rx_status = tsd->status_reg & SPI_RX_UNF; in tegra_sflash_isr()
407 tegra_sflash_clear_status(tsd); in tegra_sflash_isr()
409 return handle_cpu_based_xfer(tsd); in tegra_sflash_isr()
421 struct tegra_sflash_data *tsd; in tegra_sflash_probe() local
431 master = spi_alloc_master(&pdev->dev, sizeof(*tsd)); in tegra_sflash_probe()
444 tsd = spi_master_get_devdata(master); in tegra_sflash_probe()
445 tsd->master = master; in tegra_sflash_probe()
446 tsd->dev = &pdev->dev; in tegra_sflash_probe()
447 spin_lock_init(&tsd->lock); in tegra_sflash_probe()
449 if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency", in tegra_sflash_probe()
453 tsd->base = devm_platform_ioremap_resource(pdev, 0); in tegra_sflash_probe()
454 if (IS_ERR(tsd->base)) { in tegra_sflash_probe()
455 ret = PTR_ERR(tsd->base); in tegra_sflash_probe()
459 tsd->irq = platform_get_irq(pdev, 0); in tegra_sflash_probe()
460 ret = request_irq(tsd->irq, tegra_sflash_isr, 0, in tegra_sflash_probe()
461 dev_name(&pdev->dev), tsd); in tegra_sflash_probe()
464 tsd->irq); in tegra_sflash_probe()
468 tsd->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sflash_probe()
469 if (IS_ERR(tsd->clk)) { in tegra_sflash_probe()
471 ret = PTR_ERR(tsd->clk); in tegra_sflash_probe()
475 tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_sflash_probe()
476 if (IS_ERR(tsd->rst)) { in tegra_sflash_probe()
478 ret = PTR_ERR(tsd->rst); in tegra_sflash_probe()
482 init_completion(&tsd->xfer_completion); in tegra_sflash_probe()
498 reset_control_assert(tsd->rst); in tegra_sflash_probe()
500 reset_control_deassert(tsd->rst); in tegra_sflash_probe()
502 tsd->def_command_reg = SPI_M_S | SPI_CS_SW; in tegra_sflash_probe()
503 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); in tegra_sflash_probe()
519 free_irq(tsd->irq, tsd); in tegra_sflash_probe()
528 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); in tegra_sflash_remove() local
530 free_irq(tsd->irq, tsd); in tegra_sflash_remove()
550 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); in tegra_sflash_resume() local
558 tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND); in tegra_sflash_resume()
568 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); in tegra_sflash_runtime_suspend() local
571 tegra_sflash_readl(tsd, SPI_COMMAND); in tegra_sflash_runtime_suspend()
573 clk_disable_unprepare(tsd->clk); in tegra_sflash_runtime_suspend()
580 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); in tegra_sflash_runtime_resume() local
583 ret = clk_prepare_enable(tsd->clk); in tegra_sflash_runtime_resume()
585 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret); in tegra_sflash_runtime_resume()