Lines Matching +full:mmp2 +full:- +full:ssp
1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #include "spi-pxa2xx.h"
34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
36 MODULE_ALIAS("platform:pxa2xx-spi");
41 * for testing SSCR1 changes that require SSP restart, basically
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
104 .reg_capabilities = -1,
114 .reg_capabilities = -1,
124 .reg_capabilities = -1,
134 .reg_general = -1,
137 .reg_capabilities = -1,
144 .reg_general = -1,
157 .reg_general = -1,
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; in lpss_get_config()
178 switch (drv_data->ssp_type) { in is_lpss_ssp()
193 return drv_data->ssp_type == QUARK_X1000_SSP; in is_quark_x1000_ssp()
198 return drv_data->ssp_type == MMP2_SSP; in is_mmp2_ssp()
203 switch (drv_data->ssp_type) { in pxa2xx_spi_get_ssrc1_change_mask()
216 switch (drv_data->ssp_type) { in pxa2xx_spi_get_rx_default_thre()
230 switch (drv_data->ssp_type) { in pxa2xx_spi_txfifo_full()
250 switch (drv_data->ssp_type) { in pxa2xx_spi_clear_rx_thre()
267 switch (drv_data->ssp_type) { in pxa2xx_spi_set_rx_thre()
283 switch (drv_data->ssp_type) { in pxa2xx_configure_sscr0()
292 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) in pxa2xx_configure_sscr0()
299 * Read and write LPSS SSP private registers. Caller must first check that
304 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_read_priv()
305 return readl(drv_data->lpss_base + offset); in __lpss_ssp_read_priv()
311 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_write_priv()
312 writel(value, drv_data->lpss_base + offset); in __lpss_ssp_write_priv()
316 * lpss_ssp_setup - perform LPSS SSP specific setup
319 * Perform LPSS SSP specific setup. This function must be called first if
320 * one is going to use LPSS SSP private registers.
328 drv_data->lpss_base = drv_data->ioaddr + config->offset; in lpss_ssp_setup()
331 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_setup()
334 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_setup()
337 if (drv_data->controller_info->enable_dma) { in lpss_ssp_setup()
338 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); in lpss_ssp_setup()
340 if (config->reg_general >= 0) { in lpss_ssp_setup()
342 config->reg_general); in lpss_ssp_setup()
345 config->reg_general, value); in lpss_ssp_setup()
354 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
357 if (!config->cs_sel_mask) in lpss_ssp_select_cs()
360 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_select_cs()
362 cs = spi->chip_select; in lpss_ssp_select_cs()
363 cs <<= config->cs_sel_shift; in lpss_ssp_select_cs()
364 if (cs != (value & config->cs_sel_mask)) { in lpss_ssp_select_cs()
372 value &= ~config->cs_sel_mask; in lpss_ssp_select_cs()
375 config->reg_cs_ctrl, value); in lpss_ssp_select_cs()
377 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
384 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
393 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_cs_control()
398 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_cs_control()
399 if (config->cs_clk_stays_gated) { in lpss_ssp_cs_control()
421 spi_controller_get_devdata(spi->controller); in cs_assert()
423 if (drv_data->ssp_type == CE4100_SSP) { in cs_assert()
424 pxa2xx_spi_write(drv_data, SSSR, chip->frm); in cs_assert()
428 if (chip->cs_control) { in cs_assert()
429 chip->cs_control(PXA2XX_CS_ASSERT); in cs_assert()
433 if (chip->gpiod_cs) { in cs_assert()
434 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); in cs_assert()
446 spi_controller_get_devdata(spi->controller); in cs_deassert()
449 if (drv_data->ssp_type == CE4100_SSP) in cs_deassert()
452 /* Wait until SSP becomes idle before deasserting the CS */ in cs_deassert()
458 if (chip->cs_control) { in cs_deassert()
459 chip->cs_control(PXA2XX_CS_DEASSERT); in cs_deassert()
463 if (chip->gpiod_cs) { in cs_deassert()
464 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); in cs_deassert()
487 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
505 u8 n_bytes = drv_data->n_bytes; in null_writer()
508 || (drv_data->tx == drv_data->tx_end)) in null_writer()
512 drv_data->tx += n_bytes; in null_writer()
519 u8 n_bytes = drv_data->n_bytes; in null_reader()
522 && (drv_data->rx < drv_data->rx_end)) { in null_reader()
524 drv_data->rx += n_bytes; in null_reader()
527 return drv_data->rx == drv_data->rx_end; in null_reader()
533 || (drv_data->tx == drv_data->tx_end)) in u8_writer()
536 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); in u8_writer()
537 ++drv_data->tx; in u8_writer()
545 && (drv_data->rx < drv_data->rx_end)) { in u8_reader()
546 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
547 ++drv_data->rx; in u8_reader()
550 return drv_data->rx == drv_data->rx_end; in u8_reader()
556 || (drv_data->tx == drv_data->tx_end)) in u16_writer()
559 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); in u16_writer()
560 drv_data->tx += 2; in u16_writer()
568 && (drv_data->rx < drv_data->rx_end)) { in u16_reader()
569 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
570 drv_data->rx += 2; in u16_reader()
573 return drv_data->rx == drv_data->rx_end; in u16_reader()
579 || (drv_data->tx == drv_data->tx_end)) in u32_writer()
582 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); in u32_writer()
583 drv_data->tx += 4; in u32_writer()
591 && (drv_data->rx < drv_data->rx_end)) { in u32_reader()
592 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
593 drv_data->rx += 4; in u32_reader()
596 return drv_data->rx == drv_data->rx_end; in u32_reader()
602 spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
605 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; in reset_sccr1()
606 switch (drv_data->ssp_type) { in reset_sccr1()
617 sccr1_reg |= chip->threshold; in reset_sccr1()
623 /* Stop and reset SSP */ in int_error_stop()
624 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_error_stop()
631 dev_err(&drv_data->pdev->dev, "%s\n", msg); in int_error_stop()
633 drv_data->controller->cur_msg->status = -EIO; in int_error_stop()
634 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
640 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_transfer_complete()
645 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
651 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; in interrupt_transfer()
667 if (drv_data->read(drv_data)) { in interrupt_transfer()
675 if (drv_data->read(drv_data)) { in interrupt_transfer()
679 } while (drv_data->write(drv_data)); in interrupt_transfer()
681 if (drv_data->read(drv_data)) { in interrupt_transfer()
686 if (drv_data->tx == drv_data->tx_end) { in interrupt_transfer()
702 bytes_left = drv_data->rx_end - drv_data->rx; in interrupt_transfer()
703 switch (drv_data->n_bytes) { in interrupt_transfer()
729 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); in handle_bad_msg()
732 write_SSSR_CS(drv_data, drv_data->clear_sr); in handle_bad_msg()
734 dev_err(&drv_data->pdev->dev, in handle_bad_msg()
742 u32 mask = drv_data->mask_sr; in ssp_int()
751 if (pm_runtime_suspended(&drv_data->pdev->dev)) in ssp_int()
777 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); in ssp_int()
780 if (!drv_data->controller->cur_msg) { in ssp_int()
786 return drv_data->transfer_handler(drv_data); in ssp_int()
845 scale = fls_long(q1 - 1); in quark_x1000_get_clk_div()
847 q1 >>= scale - 9; in quark_x1000_get_clk_div()
848 mul >>= scale - 9; in quark_x1000_get_clk_div()
861 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
866 r2 = abs(fref2 / q2 - rate); in quark_x1000_get_clk_div()
896 r1 = abs(fssp - rate); in quark_x1000_get_clk_div()
907 return q - 1; in quark_x1000_get_clk_div()
912 unsigned long ssp_clk = drv_data->controller->max_speed_hz; in ssp_get_clk_div()
913 const struct ssp_device *ssp = drv_data->ssp; in ssp_get_clk_div() local
919 * that the SSP transmission rate can be greater than the device rate in ssp_get_clk_div()
921 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) in ssp_get_clk_div()
922 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; in ssp_get_clk_div()
924 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; in ssp_get_clk_div()
931 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_ssp_get_clk_div()
934 switch (drv_data->ssp_type) { in pxa2xx_ssp_get_clk_div()
936 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
951 return chip->enable_dma && in pxa2xx_spi_can_dma()
952 xfer->len <= MAX_DMA_LEN && in pxa2xx_spi_can_dma()
953 xfer->len >= chip->dma_burst_size; in pxa2xx_spi_can_dma()
961 struct spi_message *message = controller->cur_msg; in pxa2xx_spi_transfer_one()
963 u32 dma_thresh = chip->dma_threshold; in pxa2xx_spi_transfer_one()
964 u32 dma_burst = chip->dma_burst_size; in pxa2xx_spi_transfer_one()
975 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { in pxa2xx_spi_transfer_one()
977 /* reject already-mapped transfers; PIO won't always work */ in pxa2xx_spi_transfer_one()
978 if (message->is_dma_mapped in pxa2xx_spi_transfer_one()
979 || transfer->rx_dma || transfer->tx_dma) { in pxa2xx_spi_transfer_one()
980 dev_err(&spi->dev, in pxa2xx_spi_transfer_one()
982 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
983 return -EINVAL; in pxa2xx_spi_transfer_one()
987 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
989 (long)transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
994 dev_err(&spi->dev, "Flush failed\n"); in pxa2xx_spi_transfer_one()
995 return -EIO; in pxa2xx_spi_transfer_one()
997 drv_data->n_bytes = chip->n_bytes; in pxa2xx_spi_transfer_one()
998 drv_data->tx = (void *)transfer->tx_buf; in pxa2xx_spi_transfer_one()
999 drv_data->tx_end = drv_data->tx + transfer->len; in pxa2xx_spi_transfer_one()
1000 drv_data->rx = transfer->rx_buf; in pxa2xx_spi_transfer_one()
1001 drv_data->rx_end = drv_data->rx + transfer->len; in pxa2xx_spi_transfer_one()
1002 drv_data->write = drv_data->tx ? chip->write : null_writer; in pxa2xx_spi_transfer_one()
1003 drv_data->read = drv_data->rx ? chip->read : null_reader; in pxa2xx_spi_transfer_one()
1006 bits = transfer->bits_per_word; in pxa2xx_spi_transfer_one()
1007 speed = transfer->speed_hz; in pxa2xx_spi_transfer_one()
1012 drv_data->n_bytes = 1; in pxa2xx_spi_transfer_one()
1013 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1015 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1018 drv_data->n_bytes = 2; in pxa2xx_spi_transfer_one()
1019 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1021 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1024 drv_data->n_bytes = 4; in pxa2xx_spi_transfer_one()
1025 drv_data->read = drv_data->read != null_reader ? in pxa2xx_spi_transfer_one()
1027 drv_data->write = drv_data->write != null_writer ? in pxa2xx_spi_transfer_one()
1034 if (chip->enable_dma) { in pxa2xx_spi_transfer_one()
1039 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
1043 dma_mapped = controller->can_dma && in pxa2xx_spi_transfer_one()
1044 controller->can_dma(controller, spi, transfer) && in pxa2xx_spi_transfer_one()
1045 controller->cur_msg_mapped; in pxa2xx_spi_transfer_one()
1049 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; in pxa2xx_spi_transfer_one()
1056 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1057 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1062 drv_data->transfer_handler = interrupt_transfer; in pxa2xx_spi_transfer_one()
1065 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1066 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1072 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1073 controller->max_speed_hz in pxa2xx_spi_transfer_one()
1077 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1078 controller->max_speed_hz / 2 in pxa2xx_spi_transfer_one()
1084 != chip->lpss_rx_threshold) in pxa2xx_spi_transfer_one()
1086 chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1088 != chip->lpss_tx_threshold) in pxa2xx_spi_transfer_one()
1090 chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1094 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) in pxa2xx_spi_transfer_one()
1095 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); in pxa2xx_spi_transfer_one()
1101 /* stop the SSP, and update the other bits */ in pxa2xx_spi_transfer_one()
1105 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); in pxa2xx_spi_transfer_one()
1108 /* restart the SSP */ in pxa2xx_spi_transfer_one()
1113 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); in pxa2xx_spi_transfer_one()
1121 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ in pxa2xx_spi_transfer_one()
1122 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", in pxa2xx_spi_transfer_one()
1124 if (tx_level > transfer->len) in pxa2xx_spi_transfer_one()
1125 tx_level = transfer->len; in pxa2xx_spi_transfer_one()
1126 drv_data->tx += tx_level; in pxa2xx_spi_transfer_one()
1131 while (drv_data->write(drv_data)) in pxa2xx_spi_transfer_one()
1133 if (drv_data->gpiod_ready) { in pxa2xx_spi_transfer_one()
1134 gpiod_set_value(drv_data->gpiod_ready, 1); in pxa2xx_spi_transfer_one()
1136 gpiod_set_value(drv_data->gpiod_ready, 0); in pxa2xx_spi_transfer_one()
1153 /* Stop and reset SSP */ in pxa2xx_spi_slave_abort()
1154 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_slave_abort()
1161 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n"); in pxa2xx_spi_slave_abort()
1163 drv_data->controller->cur_msg->status = -EINTR; in pxa2xx_spi_slave_abort()
1164 spi_finalize_current_transfer(drv_data->controller); in pxa2xx_spi_slave_abort()
1174 /* Disable the SSP */ in pxa2xx_spi_handle_err()
1177 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_handle_err()
1180 & ~(drv_data->int_cr1 | drv_data->dma_cr1)); in pxa2xx_spi_handle_err()
1191 if (atomic_read(&drv_data->dma_running)) in pxa2xx_spi_handle_err()
1199 /* Disable the SSP now */ in pxa2xx_spi_unprepare_transfer()
1209 spi_controller_get_devdata(spi->controller); in setup_cs()
1216 if (drv_data->cs_gpiods) { in setup_cs()
1217 gpiod = drv_data->cs_gpiods[spi->chip_select]; in setup_cs()
1219 chip->gpiod_cs = gpiod; in setup_cs()
1220 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; in setup_cs()
1221 gpiod_set_value(gpiod, chip->gpio_cs_inverted); in setup_cs()
1233 if (chip->gpiod_cs) { in setup_cs()
1234 gpiod_put(chip->gpiod_cs); in setup_cs()
1235 chip->gpiod_cs = NULL; in setup_cs()
1239 if (chip_info->cs_control) { in setup_cs()
1240 chip->cs_control = chip_info->cs_control; in setup_cs()
1244 if (gpio_is_valid(chip_info->gpio_cs)) { in setup_cs()
1245 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); in setup_cs()
1247 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", in setup_cs()
1248 chip_info->gpio_cs); in setup_cs()
1252 gpiod = gpio_to_desc(chip_info->gpio_cs); in setup_cs()
1253 chip->gpiod_cs = gpiod; in setup_cs()
1254 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; in setup_cs()
1256 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); in setup_cs()
1268 spi_controller_get_devdata(spi->controller); in setup()
1271 switch (drv_data->ssp_type) { in setup()
1289 tx_thres = config->tx_threshold_lo; in setup()
1290 tx_hi_thres = config->tx_threshold_hi; in setup()
1291 rx_thres = config->rx_threshold; in setup()
1295 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1310 return -ENOMEM; in setup()
1312 if (drv_data->ssp_type == CE4100_SSP) { in setup()
1313 if (spi->chip_select > 4) { in setup()
1314 dev_err(&spi->dev, in setup()
1317 return -EINVAL; in setup()
1320 chip->frm = spi->chip_select; in setup()
1322 chip->enable_dma = drv_data->controller_info->enable_dma; in setup()
1323 chip->timeout = TIMOUT_DFLT; in setup()
1328 chip_info = spi->controller_data; in setup()
1331 chip->cr1 = 0; in setup()
1333 if (chip_info->timeout) in setup()
1334 chip->timeout = chip_info->timeout; in setup()
1335 if (chip_info->tx_threshold) in setup()
1336 tx_thres = chip_info->tx_threshold; in setup()
1337 if (chip_info->tx_hi_threshold) in setup()
1338 tx_hi_thres = chip_info->tx_hi_threshold; in setup()
1339 if (chip_info->rx_threshold) in setup()
1340 rx_thres = chip_info->rx_threshold; in setup()
1341 chip->dma_threshold = 0; in setup()
1342 if (chip_info->enable_loopback) in setup()
1343 chip->cr1 = SSCR1_LBM; in setup()
1345 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1346 chip->cr1 |= SSCR1_SCFR; in setup()
1347 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1348 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1349 chip->cr1 |= SSCR1_SPH; in setup()
1352 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); in setup()
1353 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) in setup()
1357 * chip_info goes away after setting chip->enable_dma, the in setup()
1359 if (chip->enable_dma) { in setup()
1362 spi->bits_per_word, in setup()
1363 &chip->dma_burst_size, in setup()
1364 &chip->dma_threshold)) { in setup()
1365 dev_warn(&spi->dev, in setup()
1368 dev_dbg(&spi->dev, in setup()
1370 chip->dma_burst_size); in setup()
1373 switch (drv_data->ssp_type) { in setup()
1375 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
1381 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
1385 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | in setup()
1390 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1391 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) in setup()
1392 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); in setup()
1394 if (spi->mode & SPI_LOOP) in setup()
1395 chip->cr1 |= SSCR1_LBM; in setup()
1397 if (spi->bits_per_word <= 8) { in setup()
1398 chip->n_bytes = 1; in setup()
1399 chip->read = u8_reader; in setup()
1400 chip->write = u8_writer; in setup()
1401 } else if (spi->bits_per_word <= 16) { in setup()
1402 chip->n_bytes = 2; in setup()
1403 chip->read = u16_reader; in setup()
1404 chip->write = u16_writer; in setup()
1405 } else if (spi->bits_per_word <= 32) { in setup()
1406 chip->n_bytes = 4; in setup()
1407 chip->read = u32_reader; in setup()
1408 chip->write = u32_writer; in setup()
1413 if (drv_data->ssp_type == CE4100_SSP) in setup()
1423 spi_controller_get_devdata(spi->controller); in cleanup()
1428 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && in cleanup()
1429 chip->gpiod_cs) in cleanup()
1430 gpiod_put(chip->gpiod_cs); in cleanup()
1451 * autoloading and probing in this module but matching the LPSS SSP type.
1454 /* SPT-LP */
1457 /* SPT-H */
1460 /* KBL-H */
1463 /* CML-V */
1466 /* BXT A-Step */
1470 /* BXT B-Step */
1478 /* ICL-LP */
1490 /* TGL-H */
1499 /* CNL-LP */
1503 /* CNL-H */
1507 /* CML-LP */
1511 /* CML-H */
1515 /* TGL-LP */
1527 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1538 int port_id = -1; in pxa2xx_spi_get_port_id()
1541 if (adev && adev->pnp.unique_id && in pxa2xx_spi_get_port_id()
1542 !kstrtouint(adev->pnp.unique_id, 0, &devid)) in pxa2xx_spi_get_port_id()
1551 return -1; in pxa2xx_spi_get_port_id()
1561 return param == chan->device->dev; in pxa2xx_spi_idma_filter()
1570 struct ssp_device *ssp; in pxa2xx_spi_init_pdata() local
1572 struct device *parent = pdev->dev.parent; in pxa2xx_spi_init_pdata()
1581 match = device_get_match_data(&pdev->dev); in pxa2xx_spi_init_pdata()
1585 type = (enum pxa_ssp_type)pcidev_id->driver_data; in pxa2xx_spi_init_pdata()
1587 return ERR_PTR(-EINVAL); in pxa2xx_spi_init_pdata()
1589 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in pxa2xx_spi_init_pdata()
1591 return ERR_PTR(-ENOMEM); in pxa2xx_spi_init_pdata()
1593 ssp = &pdata->ssp; in pxa2xx_spi_init_pdata()
1596 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); in pxa2xx_spi_init_pdata()
1597 if (IS_ERR(ssp->mmio_base)) in pxa2xx_spi_init_pdata()
1598 return ERR_CAST(ssp->mmio_base); in pxa2xx_spi_init_pdata()
1600 ssp->phys_base = res->start; in pxa2xx_spi_init_pdata()
1604 pdata->tx_param = parent; in pxa2xx_spi_init_pdata()
1605 pdata->rx_param = parent; in pxa2xx_spi_init_pdata()
1606 pdata->dma_filter = pxa2xx_spi_idma_filter; in pxa2xx_spi_init_pdata()
1610 ssp->clk = devm_clk_get(&pdev->dev, NULL); in pxa2xx_spi_init_pdata()
1611 if (IS_ERR(ssp->clk)) in pxa2xx_spi_init_pdata()
1612 return ERR_CAST(ssp->clk); in pxa2xx_spi_init_pdata()
1614 ssp->irq = platform_get_irq(pdev, 0); in pxa2xx_spi_init_pdata()
1615 if (ssp->irq < 0) in pxa2xx_spi_init_pdata()
1616 return ERR_PTR(ssp->irq); in pxa2xx_spi_init_pdata()
1618 ssp->type = type; in pxa2xx_spi_init_pdata()
1619 ssp->dev = &pdev->dev; in pxa2xx_spi_init_pdata()
1620 ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev); in pxa2xx_spi_init_pdata()
1622 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); in pxa2xx_spi_init_pdata()
1623 pdata->num_chipselect = 1; in pxa2xx_spi_init_pdata()
1624 pdata->enable_dma = true; in pxa2xx_spi_init_pdata()
1625 pdata->dma_burst_size = 1; in pxa2xx_spi_init_pdata()
1635 if (has_acpi_companion(&drv_data->pdev->dev)) { in pxa2xx_spi_fw_translate_cs()
1636 switch (drv_data->ssp_type) { in pxa2xx_spi_fw_translate_cs()
1644 return cs - 1; in pxa2xx_spi_fw_translate_cs()
1661 struct device *dev = &pdev->dev; in pxa2xx_spi_probe()
1665 struct ssp_device *ssp; in pxa2xx_spi_probe() local
1674 dev_err(&pdev->dev, "missing platform data\n"); in pxa2xx_spi_probe()
1679 ssp = pxa_ssp_request(pdev->id, pdev->name); in pxa2xx_spi_probe()
1680 if (!ssp) in pxa2xx_spi_probe()
1681 ssp = &platform_info->ssp; in pxa2xx_spi_probe()
1683 if (!ssp->mmio_base) { in pxa2xx_spi_probe()
1684 dev_err(&pdev->dev, "failed to get ssp\n"); in pxa2xx_spi_probe()
1685 return -ENODEV; in pxa2xx_spi_probe()
1688 if (platform_info->is_slave) in pxa2xx_spi_probe()
1694 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); in pxa2xx_spi_probe()
1695 pxa_ssp_free(ssp); in pxa2xx_spi_probe()
1696 return -ENOMEM; in pxa2xx_spi_probe()
1699 drv_data->controller = controller; in pxa2xx_spi_probe()
1700 drv_data->controller_info = platform_info; in pxa2xx_spi_probe()
1701 drv_data->pdev = pdev; in pxa2xx_spi_probe()
1702 drv_data->ssp = ssp; in pxa2xx_spi_probe()
1704 controller->dev.of_node = pdev->dev.of_node; in pxa2xx_spi_probe()
1705 /* the spi->mode bits understood by this driver: */ in pxa2xx_spi_probe()
1706 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pxa2xx_spi_probe()
1708 controller->bus_num = ssp->port_id; in pxa2xx_spi_probe()
1709 controller->dma_alignment = DMA_ALIGNMENT; in pxa2xx_spi_probe()
1710 controller->cleanup = cleanup; in pxa2xx_spi_probe()
1711 controller->setup = setup; in pxa2xx_spi_probe()
1712 controller->set_cs = pxa2xx_spi_set_cs; in pxa2xx_spi_probe()
1713 controller->transfer_one = pxa2xx_spi_transfer_one; in pxa2xx_spi_probe()
1714 controller->slave_abort = pxa2xx_spi_slave_abort; in pxa2xx_spi_probe()
1715 controller->handle_err = pxa2xx_spi_handle_err; in pxa2xx_spi_probe()
1716 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; in pxa2xx_spi_probe()
1717 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; in pxa2xx_spi_probe()
1718 controller->auto_runtime_pm = true; in pxa2xx_spi_probe()
1719 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in pxa2xx_spi_probe()
1721 drv_data->ssp_type = ssp->type; in pxa2xx_spi_probe()
1723 drv_data->ioaddr = ssp->mmio_base; in pxa2xx_spi_probe()
1724 drv_data->ssdr_physical = ssp->phys_base + SSDR; in pxa2xx_spi_probe()
1726 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1728 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1731 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in pxa2xx_spi_probe()
1735 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1736 drv_data->dma_cr1 = 0; in pxa2xx_spi_probe()
1737 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()
1738 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()
1740 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1741 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
1742 drv_data->dma_cr1 = DEFAULT_DMA_CR1; in pxa2xx_spi_probe()
1743 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()
1744 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS in pxa2xx_spi_probe()
1748 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), in pxa2xx_spi_probe()
1751 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); in pxa2xx_spi_probe()
1756 if (platform_info->enable_dma) { in pxa2xx_spi_probe()
1760 platform_info->enable_dma = false; in pxa2xx_spi_probe()
1762 controller->can_dma = pxa2xx_spi_can_dma; in pxa2xx_spi_probe()
1763 controller->max_dma_len = MAX_DMA_LEN; in pxa2xx_spi_probe()
1764 controller->max_transfer_size = in pxa2xx_spi_probe()
1770 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_probe()
1774 controller->max_speed_hz = clk_get_rate(ssp->clk); in pxa2xx_spi_probe()
1780 controller->min_speed_hz = in pxa2xx_spi_probe()
1781 DIV_ROUND_UP(controller->max_speed_hz, 4096); in pxa2xx_spi_probe()
1783 controller->min_speed_hz = in pxa2xx_spi_probe()
1784 DIV_ROUND_UP(controller->max_speed_hz, 512); in pxa2xx_spi_probe()
1786 /* Load default SSP configuration */ in pxa2xx_spi_probe()
1788 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1835 if (config->reg_capabilities >= 0) { in pxa2xx_spi_probe()
1837 config->reg_capabilities); in pxa2xx_spi_probe()
1840 platform_info->num_chipselect = ffz(tmp); in pxa2xx_spi_probe()
1841 } else if (config->cs_num) { in pxa2xx_spi_probe()
1842 platform_info->num_chipselect = config->cs_num; in pxa2xx_spi_probe()
1845 controller->num_chipselect = platform_info->num_chipselect; in pxa2xx_spi_probe()
1847 count = gpiod_count(&pdev->dev, "cs"); in pxa2xx_spi_probe()
1851 controller->num_chipselect = max_t(int, count, in pxa2xx_spi_probe()
1852 controller->num_chipselect); in pxa2xx_spi_probe()
1854 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, in pxa2xx_spi_probe()
1855 controller->num_chipselect, sizeof(struct gpio_desc *), in pxa2xx_spi_probe()
1857 if (!drv_data->cs_gpiods) { in pxa2xx_spi_probe()
1858 status = -ENOMEM; in pxa2xx_spi_probe()
1862 for (i = 0; i < controller->num_chipselect; i++) { in pxa2xx_spi_probe()
1868 if (PTR_ERR(gpiod) == -ENOENT) in pxa2xx_spi_probe()
1874 drv_data->cs_gpiods[i] = gpiod; in pxa2xx_spi_probe()
1879 if (platform_info->is_slave) { in pxa2xx_spi_probe()
1880 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, in pxa2xx_spi_probe()
1882 if (IS_ERR(drv_data->gpiod_ready)) { in pxa2xx_spi_probe()
1883 status = PTR_ERR(drv_data->gpiod_ready); in pxa2xx_spi_probe()
1888 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in pxa2xx_spi_probe()
1889 pm_runtime_use_autosuspend(&pdev->dev); in pxa2xx_spi_probe()
1890 pm_runtime_set_active(&pdev->dev); in pxa2xx_spi_probe()
1891 pm_runtime_enable(&pdev->dev); in pxa2xx_spi_probe()
1897 dev_err(&pdev->dev, "problem registering spi controller\n"); in pxa2xx_spi_probe()
1904 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_probe()
1907 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_probe()
1911 free_irq(ssp->irq, drv_data); in pxa2xx_spi_probe()
1915 pxa_ssp_free(ssp); in pxa2xx_spi_probe()
1922 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_remove() local
1924 pm_runtime_get_sync(&pdev->dev); in pxa2xx_spi_remove()
1926 spi_unregister_controller(drv_data->controller); in pxa2xx_spi_remove()
1928 /* Disable the SSP at the peripheral and SOC level */ in pxa2xx_spi_remove()
1930 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_remove()
1933 if (drv_data->controller_info->enable_dma) in pxa2xx_spi_remove()
1936 pm_runtime_put_noidle(&pdev->dev); in pxa2xx_spi_remove()
1937 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_remove()
1940 free_irq(ssp->irq, drv_data); in pxa2xx_spi_remove()
1942 /* Release SSP */ in pxa2xx_spi_remove()
1943 pxa_ssp_free(ssp); in pxa2xx_spi_remove()
1952 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_suspend() local
1955 status = spi_controller_suspend(drv_data->controller); in pxa2xx_spi_suspend()
1961 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_suspend()
1969 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_resume() local
1972 /* Enable the SSP clock */ in pxa2xx_spi_resume()
1974 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_resume()
1980 return spi_controller_resume(drv_data->controller); in pxa2xx_spi_resume()
1989 clk_disable_unprepare(drv_data->ssp->clk); in pxa2xx_spi_runtime_suspend()
1998 status = clk_prepare_enable(drv_data->ssp->clk); in pxa2xx_spi_runtime_resume()
2011 .name = "pxa2xx-spi",