Lines Matching +full:sg +full:- +full:micro
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008-2012 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 #include <linux/dma-mapping.h>
93 * SSP Control Register 0 - SSP_CR0
111 * SSP Control Register 0 - SSP_CR1
131 * SSP Status Register - SSP_SR
140 * SSP Clock Prescale Register - SSP_CPSR
145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
153 * SSP Raw Interrupt Status Register - SSP_RIS
165 * SSP Masked Interrupt Status Register - SSP_MIS
177 * SSP Interrupt Clear Register - SSP_ICR
185 * SSP DMA Control Register - SSP_DMACR
193 * SSP Chip Select Control Register - SSP_CSR
199 * SSP Integration Test control Register - SSP_ITCR
205 * SSP Integration Test Input Register - SSP_ITIP
215 * SSP Integration Test output Register - SSP_ITOP
233 * SSP Test Data Register - SSP_TDR
246 #define STATE_ERROR ((void *) -1)
247 #define STATE_TIMEOUT ((void *) -2)
250 * SSP State - Whether Enabled or Disabled
256 * SSP DMA State - Whether DMA Enabled or Disabled
312 * struct vendor_data - vendor-specific config parameters
334 * struct pl022 - This is the private SSP driver data structure
341 * @master_info: controller-specific data from machine setup
376 /* Message per-transfer pump */
405 * struct chip_data - To maintain runtime state of SSP for each client chip
406 * @cr0: Value of control register CR0 of SSP - on later ST variants this
435 * null_cs_control - Dummy chip select function
447 * internal_cs_control - Control chip select signals via SSP_CSR.
459 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
461 tmp &= ~BIT(pl022->cur_cs); in internal_cs_control()
463 tmp |= BIT(pl022->cur_cs); in internal_cs_control()
464 writew(tmp, SSP_CSR(pl022->virtbase)); in internal_cs_control()
469 if (pl022->vendor->internal_cs_ctrl) in pl022_cs_control()
471 else if (gpio_is_valid(pl022->cur_cs)) in pl022_cs_control()
472 gpio_set_value(pl022->cur_cs, command); in pl022_cs_control()
474 pl022->cur_chip->cs_control(command); in pl022_cs_control()
478 * giveback - current spi_message is over, schedule next message and call
480 * set message->status; dma and pio irqs are blocked
486 pl022->next_msg_cs_active = false; in giveback()
488 last_transfer = list_last_entry(&pl022->cur_msg->transfers, in giveback()
498 if (!last_transfer->cs_change) { in giveback()
507 * after calling msg->complete (below) the driver that in giveback()
512 next_msg = spi_get_next_queued_message(pl022->master); in giveback()
518 if (next_msg && next_msg->spi != pl022->cur_msg->spi) in giveback()
520 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) in giveback()
523 pl022->next_msg_cs_active = true; in giveback()
527 pl022->cur_msg = NULL; in giveback()
528 pl022->cur_transfer = NULL; in giveback()
529 pl022->cur_chip = NULL; in giveback()
532 writew((readw(SSP_CR1(pl022->virtbase)) & in giveback()
533 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in giveback()
535 spi_finalize_current_message(pl022->master); in giveback()
539 * flush - flush the FIFO to reach a clean state
546 dev_dbg(&pl022->adev->dev, "flush\n"); in flush()
548 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
549 readw(SSP_DR(pl022->virtbase)); in flush()
550 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
552 pl022->exp_fifo_level = 0; in flush()
558 * restore_state - Load configuration of current chip
563 struct chip_data *chip = pl022->cur_chip; in restore_state()
565 if (pl022->vendor->extended_cr) in restore_state()
566 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
568 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
569 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
570 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
571 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); in restore_state()
572 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in restore_state()
573 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in restore_state()
648 * load_ssp_default_config - Load default configuration for SSP
653 if (pl022->vendor->pl023) { in load_ssp_default_config()
654 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
655 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
656 } else if (pl022->vendor->extended_cr) { in load_ssp_default_config()
657 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
658 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
660 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
661 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
663 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); in load_ssp_default_config()
664 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); in load_ssp_default_config()
665 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in load_ssp_default_config()
666 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in load_ssp_default_config()
686 dev_dbg(&pl022->adev->dev, in readwriter()
688 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); in readwriter()
691 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
692 && (pl022->rx < pl022->rx_end)) { in readwriter()
693 switch (pl022->read) { in readwriter()
695 readw(SSP_DR(pl022->virtbase)); in readwriter()
698 *(u8 *) (pl022->rx) = in readwriter()
699 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
702 *(u16 *) (pl022->rx) = in readwriter()
703 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
706 *(u32 *) (pl022->rx) = in readwriter()
707 readl(SSP_DR(pl022->virtbase)); in readwriter()
710 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
711 pl022->exp_fifo_level--; in readwriter()
716 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) in readwriter()
717 && (pl022->tx < pl022->tx_end)) { in readwriter()
718 switch (pl022->write) { in readwriter()
720 writew(0x0, SSP_DR(pl022->virtbase)); in readwriter()
723 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
726 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); in readwriter()
729 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
732 pl022->tx += (pl022->cur_chip->n_bytes); in readwriter()
733 pl022->exp_fifo_level++; in readwriter()
740 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
741 && (pl022->rx < pl022->rx_end)) { in readwriter()
742 switch (pl022->read) { in readwriter()
744 readw(SSP_DR(pl022->virtbase)); in readwriter()
747 *(u8 *) (pl022->rx) = in readwriter()
748 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
751 *(u16 *) (pl022->rx) = in readwriter()
752 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
755 *(u32 *) (pl022->rx) = in readwriter()
756 readl(SSP_DR(pl022->virtbase)); in readwriter()
759 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
760 pl022->exp_fifo_level--; in readwriter()
770 * next_transfer - Move to the Next transfer in the current spi message
780 struct spi_message *msg = pl022->cur_msg; in next_transfer()
781 struct spi_transfer *trans = pl022->cur_transfer; in next_transfer()
784 if (trans->transfer_list.next != &msg->transfers) { in next_transfer()
785 pl022->cur_transfer = in next_transfer()
786 list_entry(trans->transfer_list.next, in next_transfer()
800 /* Unmap and free the SG tables */ in unmap_free_dma_scatter()
801 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, in unmap_free_dma_scatter()
802 pl022->sgt_tx.nents, DMA_TO_DEVICE); in unmap_free_dma_scatter()
803 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, in unmap_free_dma_scatter()
804 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in unmap_free_dma_scatter()
805 sg_free_table(&pl022->sgt_rx); in unmap_free_dma_scatter()
806 sg_free_table(&pl022->sgt_tx); in unmap_free_dma_scatter()
812 struct spi_message *msg = pl022->cur_msg; in dma_callback()
814 BUG_ON(!pl022->sgt_rx.sgl); in dma_callback()
824 struct scatterlist *sg; in dma_callback() local
827 dma_sync_sg_for_cpu(&pl022->adev->dev, in dma_callback()
828 pl022->sgt_rx.sgl, in dma_callback()
829 pl022->sgt_rx.nents, in dma_callback()
832 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { in dma_callback()
833 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); in dma_callback()
838 sg_virt(sg), in dma_callback()
839 sg_dma_len(sg), in dma_callback()
842 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { in dma_callback()
843 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); in dma_callback()
848 sg_virt(sg), in dma_callback()
849 sg_dma_len(sg), in dma_callback()
858 msg->actual_length += pl022->cur_transfer->len; in dma_callback()
860 msg->state = next_transfer(pl022); in dma_callback()
861 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) in dma_callback()
863 tasklet_schedule(&pl022->pump_transfers); in dma_callback()
871 struct scatterlist *sg; in setup_dma_scatter() local
878 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
885 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) in setup_dma_scatter()
888 mapbytes = PAGE_SIZE - offset_in_page(bufp); in setup_dma_scatter()
889 sg_set_page(sg, virt_to_page(bufp), in setup_dma_scatter()
892 bytesleft -= mapbytes; in setup_dma_scatter()
893 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
899 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
904 sg_set_page(sg, virt_to_page(pl022->dummypage), in setup_dma_scatter()
906 bytesleft -= mapbytes; in setup_dma_scatter()
907 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
917 * configure_dma - configures the channels for the next transfer
923 .src_addr = SSP_DR(pl022->phybase), in configure_dma()
928 .dst_addr = SSP_DR(pl022->phybase), in configure_dma()
935 struct dma_chan *rxchan = pl022->dma_rx_channel; in configure_dma()
936 struct dma_chan *txchan = pl022->dma_tx_channel; in configure_dma()
942 return -ENODEV; in configure_dma()
946 * Notice that the DMA engine uses one-to-one mapping. Since we can in configure_dma()
950 switch (pl022->rx_lev_trig) { in configure_dma()
967 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
971 switch (pl022->tx_lev_trig) { in configure_dma()
988 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
992 switch (pl022->read) { in configure_dma()
1008 switch (pl022->write) { in configure_dma()
1035 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); in configure_dma()
1036 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); in configure_dma()
1038 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); in configure_dma()
1042 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); in configure_dma()
1047 setup_dma_scatter(pl022, pl022->rx, in configure_dma()
1048 pl022->cur_transfer->len, &pl022->sgt_rx); in configure_dma()
1049 setup_dma_scatter(pl022, pl022->tx, in configure_dma()
1050 pl022->cur_transfer->len, &pl022->sgt_tx); in configure_dma()
1053 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1054 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1058 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1059 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1065 pl022->sgt_rx.sgl, in configure_dma()
1073 pl022->sgt_tx.sgl, in configure_dma()
1081 rxdesc->callback = dma_callback; in configure_dma()
1082 rxdesc->callback_param = pl022; in configure_dma()
1089 pl022->dma_running = true; in configure_dma()
1097 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1098 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1100 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1101 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1103 sg_free_table(&pl022->sgt_tx); in configure_dma()
1105 sg_free_table(&pl022->sgt_rx); in configure_dma()
1107 return -ENOMEM; in configure_dma()
1121 pl022->dma_rx_channel = dma_request_channel(mask, in pl022_dma_probe()
1122 pl022->master_info->dma_filter, in pl022_dma_probe()
1123 pl022->master_info->dma_rx_param); in pl022_dma_probe()
1124 if (!pl022->dma_rx_channel) { in pl022_dma_probe()
1125 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); in pl022_dma_probe()
1129 pl022->dma_tx_channel = dma_request_channel(mask, in pl022_dma_probe()
1130 pl022->master_info->dma_filter, in pl022_dma_probe()
1131 pl022->master_info->dma_tx_param); in pl022_dma_probe()
1132 if (!pl022->dma_tx_channel) { in pl022_dma_probe()
1133 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); in pl022_dma_probe()
1137 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_probe()
1138 if (!pl022->dummypage) in pl022_dma_probe()
1141 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", in pl022_dma_probe()
1142 dma_chan_name(pl022->dma_rx_channel), in pl022_dma_probe()
1143 dma_chan_name(pl022->dma_tx_channel)); in pl022_dma_probe()
1148 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_probe()
1150 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_probe()
1151 pl022->dma_rx_channel = NULL; in pl022_dma_probe()
1153 dev_err(&pl022->adev->dev, in pl022_dma_probe()
1155 return -ENODEV; in pl022_dma_probe()
1160 struct device *dev = &pl022->adev->dev; in pl022_dma_autoprobe()
1171 pl022->dma_rx_channel = chan; in pl022_dma_autoprobe()
1179 pl022->dma_tx_channel = chan; in pl022_dma_autoprobe()
1181 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_autoprobe()
1182 if (!pl022->dummypage) { in pl022_dma_autoprobe()
1183 err = -ENOMEM; in pl022_dma_autoprobe()
1190 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_autoprobe()
1191 pl022->dma_tx_channel = NULL; in pl022_dma_autoprobe()
1193 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_autoprobe()
1194 pl022->dma_rx_channel = NULL; in pl022_dma_autoprobe()
1201 struct dma_chan *rxchan = pl022->dma_rx_channel; in terminate_dma()
1202 struct dma_chan *txchan = pl022->dma_tx_channel; in terminate_dma()
1207 pl022->dma_running = false; in terminate_dma()
1212 if (pl022->dma_running) in pl022_dma_remove()
1214 if (pl022->dma_tx_channel) in pl022_dma_remove()
1215 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_remove()
1216 if (pl022->dma_rx_channel) in pl022_dma_remove()
1217 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_remove()
1218 kfree(pl022->dummypage); in pl022_dma_remove()
1224 return -ENODEV; in configure_dma()
1243 * pl022_interrupt_handler - Interrupt handler for SSP controller
1258 struct spi_message *msg = pl022->cur_msg; in pl022_interrupt_handler()
1262 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1269 irq_status = readw(SSP_MIS(pl022->virtbase)); in pl022_interrupt_handler()
1281 * Overrun interrupt - bail out since our Data has been in pl022_interrupt_handler()
1284 dev_err(&pl022->adev->dev, "FIFO overrun\n"); in pl022_interrupt_handler()
1285 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) in pl022_interrupt_handler()
1286 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1295 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1296 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1297 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1298 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_interrupt_handler()
1299 msg->state = STATE_ERROR; in pl022_interrupt_handler()
1302 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1308 if (pl022->tx == pl022->tx_end) { in pl022_interrupt_handler()
1310 writew((readw(SSP_IMSC(pl022->virtbase)) & in pl022_interrupt_handler()
1312 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1320 if (pl022->rx >= pl022->rx_end) { in pl022_interrupt_handler()
1322 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1323 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1324 if (unlikely(pl022->rx > pl022->rx_end)) { in pl022_interrupt_handler()
1325 dev_warn(&pl022->adev->dev, "read %u surplus " in pl022_interrupt_handler()
1328 (u32) (pl022->rx - pl022->rx_end)); in pl022_interrupt_handler()
1331 msg->actual_length += pl022->cur_transfer->len; in pl022_interrupt_handler()
1333 msg->state = next_transfer(pl022); in pl022_interrupt_handler()
1334 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) in pl022_interrupt_handler()
1336 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1353 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; in set_up_next_transfer()
1355 dev_err(&pl022->adev->dev, in set_up_next_transfer()
1358 pl022->cur_transfer->len, in set_up_next_transfer()
1359 pl022->cur_chip->n_bytes); in set_up_next_transfer()
1360 dev_err(&pl022->adev->dev, "skipping this message\n"); in set_up_next_transfer()
1361 return -EIO; in set_up_next_transfer()
1363 pl022->tx = (void *)transfer->tx_buf; in set_up_next_transfer()
1364 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; in set_up_next_transfer()
1365 pl022->rx = (void *)transfer->rx_buf; in set_up_next_transfer()
1366 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; in set_up_next_transfer()
1367 pl022->write = in set_up_next_transfer()
1368 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; in set_up_next_transfer()
1369 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; in set_up_next_transfer()
1374 * pump_transfers - Tasklet function which schedules next transfer
1387 message = pl022->cur_msg; in pump_transfers()
1388 transfer = pl022->cur_transfer; in pump_transfers()
1391 if (message->state == STATE_ERROR) { in pump_transfers()
1392 message->status = -EIO; in pump_transfers()
1398 if (message->state == STATE_DONE) { in pump_transfers()
1399 message->status = 0; in pump_transfers()
1405 if (message->state == STATE_RUNNING) { in pump_transfers()
1406 previous = list_entry(transfer->transfer_list.prev, in pump_transfers()
1416 if (previous->cs_change) in pump_transfers()
1420 message->state = STATE_RUNNING; in pump_transfers()
1424 message->state = STATE_ERROR; in pump_transfers()
1425 message->status = -EIO; in pump_transfers()
1432 if (pl022->cur_chip->enable_dma) { in pump_transfers()
1434 dev_dbg(&pl022->adev->dev, in pump_transfers()
1443 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); in pump_transfers()
1449 * Default is to enable all interrupts except RX - in do_interrupt_dma_transfer()
1455 if (!pl022->next_msg_cs_active) in do_interrupt_dma_transfer()
1458 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { in do_interrupt_dma_transfer()
1460 pl022->cur_msg->state = STATE_ERROR; in do_interrupt_dma_transfer()
1461 pl022->cur_msg->status = -EIO; in do_interrupt_dma_transfer()
1466 if (pl022->cur_chip->enable_dma) { in do_interrupt_dma_transfer()
1469 dev_dbg(&pl022->adev->dev, in do_interrupt_dma_transfer()
1478 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_interrupt_dma_transfer()
1479 SSP_CR1(pl022->virtbase)); in do_interrupt_dma_transfer()
1480 writew(irqflags, SSP_IMSC(pl022->virtbase)); in do_interrupt_dma_transfer()
1488 if (pl022->vendor->extended_cr) in print_current_status()
1489 read_cr0 = readl(SSP_CR0(pl022->virtbase)); in print_current_status()
1491 read_cr0 = readw(SSP_CR0(pl022->virtbase)); in print_current_status()
1492 read_cr1 = readw(SSP_CR1(pl022->virtbase)); in print_current_status()
1493 read_dmacr = readw(SSP_DMACR(pl022->virtbase)); in print_current_status()
1494 read_sr = readw(SSP_SR(pl022->virtbase)); in print_current_status()
1496 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); in print_current_status()
1497 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); in print_current_status()
1498 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); in print_current_status()
1499 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); in print_current_status()
1500 dev_warn(&pl022->adev->dev, in print_current_status()
1501 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", in print_current_status()
1502 pl022->exp_fifo_level, in print_current_status()
1503 pl022->vendor->fifodepth); in print_current_status()
1514 message = pl022->cur_msg; in do_polling_transfer()
1516 while (message->state != STATE_DONE) { in do_polling_transfer()
1518 if (message->state == STATE_ERROR) in do_polling_transfer()
1520 transfer = pl022->cur_transfer; in do_polling_transfer()
1523 if (message->state == STATE_RUNNING) { in do_polling_transfer()
1525 list_entry(transfer->transfer_list.prev, in do_polling_transfer()
1528 if (previous->cs_change) in do_polling_transfer()
1532 message->state = STATE_RUNNING; in do_polling_transfer()
1533 if (!pl022->next_msg_cs_active) in do_polling_transfer()
1540 message->state = STATE_ERROR; in do_polling_transfer()
1545 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_polling_transfer()
1546 SSP_CR1(pl022->virtbase)); in do_polling_transfer()
1548 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); in do_polling_transfer()
1551 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { in do_polling_transfer()
1555 dev_warn(&pl022->adev->dev, in do_polling_transfer()
1557 message->state = STATE_TIMEOUT; in do_polling_transfer()
1565 message->actual_length += pl022->cur_transfer->len; in do_polling_transfer()
1567 message->state = next_transfer(pl022); in do_polling_transfer()
1568 if (message->state != STATE_DONE in do_polling_transfer()
1569 && pl022->cur_transfer->cs_change) in do_polling_transfer()
1574 if (message->state == STATE_DONE) in do_polling_transfer()
1575 message->status = 0; in do_polling_transfer()
1576 else if (message->state == STATE_TIMEOUT) in do_polling_transfer()
1577 message->status = -EAGAIN; in do_polling_transfer()
1579 message->status = -EIO; in do_polling_transfer()
1591 pl022->cur_msg = msg; in pl022_transfer_one_message()
1592 msg->state = STATE_START; in pl022_transfer_one_message()
1594 pl022->cur_transfer = list_entry(msg->transfers.next, in pl022_transfer_one_message()
1598 pl022->cur_chip = spi_get_ctldata(msg->spi); in pl022_transfer_one_message()
1599 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; in pl022_transfer_one_message()
1604 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) in pl022_transfer_one_message()
1616 /* nothing more to do - disable spi/ssp and power off */ in pl022_unprepare_transfer_hardware()
1617 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_unprepare_transfer_hardware()
1618 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_unprepare_transfer_hardware()
1626 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) in verify_controller_parameters()
1627 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { in verify_controller_parameters()
1628 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1630 return -EINVAL; in verify_controller_parameters()
1632 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && in verify_controller_parameters()
1633 (!pl022->vendor->unidir)) { in verify_controller_parameters()
1634 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1637 return -EINVAL; in verify_controller_parameters()
1639 if ((chip_info->hierarchy != SSP_MASTER) in verify_controller_parameters()
1640 && (chip_info->hierarchy != SSP_SLAVE)) { in verify_controller_parameters()
1641 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1643 return -EINVAL; in verify_controller_parameters()
1645 if ((chip_info->com_mode != INTERRUPT_TRANSFER) in verify_controller_parameters()
1646 && (chip_info->com_mode != DMA_TRANSFER) in verify_controller_parameters()
1647 && (chip_info->com_mode != POLLING_TRANSFER)) { in verify_controller_parameters()
1648 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1650 return -EINVAL; in verify_controller_parameters()
1652 switch (chip_info->rx_lev_trig) { in verify_controller_parameters()
1659 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1660 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1662 return -EINVAL; in verify_controller_parameters()
1666 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1667 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1669 return -EINVAL; in verify_controller_parameters()
1673 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1675 return -EINVAL; in verify_controller_parameters()
1677 switch (chip_info->tx_lev_trig) { in verify_controller_parameters()
1684 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1685 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1687 return -EINVAL; in verify_controller_parameters()
1691 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1692 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1694 return -EINVAL; in verify_controller_parameters()
1698 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1700 return -EINVAL; in verify_controller_parameters()
1702 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { in verify_controller_parameters()
1703 if ((chip_info->ctrl_len < SSP_BITS_4) in verify_controller_parameters()
1704 || (chip_info->ctrl_len > SSP_BITS_32)) { in verify_controller_parameters()
1705 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1707 return -EINVAL; in verify_controller_parameters()
1709 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) in verify_controller_parameters()
1710 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { in verify_controller_parameters()
1711 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1713 return -EINVAL; in verify_controller_parameters()
1715 /* Half duplex is only available in the ST Micro version */ in verify_controller_parameters()
1716 if (pl022->vendor->extended_cr) { in verify_controller_parameters()
1717 if ((chip_info->duplex != in verify_controller_parameters()
1719 && (chip_info->duplex != in verify_controller_parameters()
1721 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1723 return -EINVAL; in verify_controller_parameters()
1726 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) in verify_controller_parameters()
1727 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1731 return -EINVAL; in verify_controller_parameters()
1750 rate = clk_get_rate(pl022->clk); in calculate_effective_freq()
1757 dev_warn(&pl022->adev->dev, in calculate_effective_freq()
1762 dev_err(&pl022->adev->dev, in calculate_effective_freq()
1765 return -EINVAL; in calculate_effective_freq()
1807 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1808 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1809 dev_dbg(&pl022->adev->dev, in calculate_effective_freq()
1812 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1813 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1836 * pl022_setup - setup function registered to SPI master framework
1854 struct pl022 *pl022 = spi_master_get_devdata(spi->master); in pl022_setup()
1855 unsigned int bits = spi->bits_per_word; in pl022_setup()
1857 struct device_node *np = spi->dev.of_node; in pl022_setup()
1859 if (!spi->max_speed_hz) in pl022_setup()
1860 return -EINVAL; in pl022_setup()
1868 return -ENOMEM; in pl022_setup()
1869 dev_dbg(&spi->dev, in pl022_setup()
1874 chip_info = spi->controller_data; in pl022_setup()
1883 of_property_read_u32(np, "pl022,com-mode", in pl022_setup()
1885 of_property_read_u32(np, "pl022,rx-level-trig", in pl022_setup()
1887 of_property_read_u32(np, "pl022,tx-level-trig", in pl022_setup()
1889 of_property_read_u32(np, "pl022,ctrl-len", in pl022_setup()
1891 of_property_read_u32(np, "pl022,wait-state", in pl022_setup()
1900 dev_dbg(&spi->dev, in pl022_setup()
1904 dev_dbg(&spi->dev, in pl022_setup()
1911 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1912 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1914 spi->max_speed_hz, in pl022_setup()
1919 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1922 clk_freq.cpsdvsr - 1; in pl022_setup()
1926 status = -EINVAL; in pl022_setup()
1927 dev_err(&spi->dev, in pl022_setup()
1934 dev_err(&spi->dev, "controller data is incorrect"); in pl022_setup()
1938 pl022->rx_lev_trig = chip_info->rx_lev_trig; in pl022_setup()
1939 pl022->tx_lev_trig = chip_info->tx_lev_trig; in pl022_setup()
1942 chip->xfer_type = chip_info->com_mode; in pl022_setup()
1943 if (!chip_info->cs_control) { in pl022_setup()
1944 chip->cs_control = null_cs_control; in pl022_setup()
1945 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) in pl022_setup()
1946 dev_warn(&spi->dev, in pl022_setup()
1949 chip->cs_control = chip_info->cs_control; in pl022_setup()
1952 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { in pl022_setup()
1953 status = -ENOTSUPP; in pl022_setup()
1954 dev_err(&spi->dev, "illegal data size for this controller!\n"); in pl022_setup()
1955 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", in pl022_setup()
1956 pl022->vendor->max_bpw); in pl022_setup()
1959 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); in pl022_setup()
1960 chip->n_bytes = 1; in pl022_setup()
1961 chip->read = READING_U8; in pl022_setup()
1962 chip->write = WRITING_U8; in pl022_setup()
1964 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); in pl022_setup()
1965 chip->n_bytes = 2; in pl022_setup()
1966 chip->read = READING_U16; in pl022_setup()
1967 chip->write = WRITING_U16; in pl022_setup()
1969 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); in pl022_setup()
1970 chip->n_bytes = 4; in pl022_setup()
1971 chip->read = READING_U32; in pl022_setup()
1972 chip->write = WRITING_U32; in pl022_setup()
1976 chip->cr0 = 0; in pl022_setup()
1977 chip->cr1 = 0; in pl022_setup()
1978 chip->dmacr = 0; in pl022_setup()
1979 chip->cpsr = 0; in pl022_setup()
1980 if ((chip_info->com_mode == DMA_TRANSFER) in pl022_setup()
1981 && ((pl022->master_info)->enable_dma)) { in pl022_setup()
1982 chip->enable_dma = true; in pl022_setup()
1983 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); in pl022_setup()
1984 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1986 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1989 chip->enable_dma = false; in pl022_setup()
1990 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); in pl022_setup()
1991 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1993 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1997 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
1999 /* Special setup for the ST micro extended control registers */ in pl022_setup()
2000 if (pl022->vendor->extended_cr) { in pl022_setup()
2003 if (pl022->vendor->pl023) { in pl022_setup()
2005 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
2009 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
2011 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
2013 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2015 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
2018 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2021 if (spi->mode & SPI_LSB_FIRST) { in pl022_setup()
2028 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2029 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2030 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2032 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2035 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2037 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2042 if (spi->mode & SPI_CPOL) in pl022_setup()
2046 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); in pl022_setup()
2048 if (spi->mode & SPI_CPHA) in pl022_setup()
2052 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); in pl022_setup()
2054 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()
2056 if (pl022->vendor->loopback) { in pl022_setup()
2057 if (spi->mode & SPI_LOOP) in pl022_setup()
2061 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
2063 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); in pl022_setup()
2064 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); in pl022_setup()
2065 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, in pl022_setup()
2078 * pl022_cleanup - cleanup function registered to SPI master framework
2095 struct device_node *np = dev->of_node; in pl022_platform_data_dt_get()
2108 pd->bus_id = -1; in pl022_platform_data_dt_get()
2109 pd->enable_dma = 1; in pl022_platform_data_dt_get()
2110 of_property_read_u32(np, "num-cs", &tmp); in pl022_platform_data_dt_get()
2111 pd->num_chipselect = tmp; in pl022_platform_data_dt_get()
2112 of_property_read_u32(np, "pl022,autosuspend-delay", in pl022_platform_data_dt_get()
2113 &pd->autosuspend_delay); in pl022_platform_data_dt_get()
2114 pd->rt = of_property_read_bool(np, "pl022,rt"); in pl022_platform_data_dt_get()
2121 struct device *dev = &adev->dev; in pl022_probe()
2123 dev_get_platdata(&adev->dev); in pl022_probe()
2126 struct device_node *np = adev->dev.of_node; in pl022_probe()
2129 dev_info(&adev->dev, in pl022_probe()
2130 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); in pl022_probe()
2136 return -ENODEV; in pl022_probe()
2139 if (platform_info->num_chipselect) { in pl022_probe()
2140 num_cs = platform_info->num_chipselect; in pl022_probe()
2143 return -ENODEV; in pl022_probe()
2149 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); in pl022_probe()
2150 return -ENOMEM; in pl022_probe()
2154 pl022->master = master; in pl022_probe()
2155 pl022->master_info = platform_info; in pl022_probe()
2156 pl022->adev = adev; in pl022_probe()
2157 pl022->vendor = id->data; in pl022_probe()
2158 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), in pl022_probe()
2160 if (!pl022->chipselects) { in pl022_probe()
2161 status = -ENOMEM; in pl022_probe()
2169 master->bus_num = platform_info->bus_id; in pl022_probe()
2170 master->num_chipselect = num_cs; in pl022_probe()
2171 master->cleanup = pl022_cleanup; in pl022_probe()
2172 master->setup = pl022_setup; in pl022_probe()
2173 master->auto_runtime_pm = true; in pl022_probe()
2174 master->transfer_one_message = pl022_transfer_one_message; in pl022_probe()
2175 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; in pl022_probe()
2176 master->rt = platform_info->rt; in pl022_probe()
2177 master->dev.of_node = dev->of_node; in pl022_probe()
2179 if (platform_info->num_chipselect && platform_info->chipselects) { in pl022_probe()
2181 pl022->chipselects[i] = platform_info->chipselects[i]; in pl022_probe()
2182 } else if (pl022->vendor->internal_cs_ctrl) { in pl022_probe()
2184 pl022->chipselects[i] = i; in pl022_probe()
2187 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); in pl022_probe()
2189 if (cs_gpio == -EPROBE_DEFER) { in pl022_probe()
2190 status = -EPROBE_DEFER; in pl022_probe()
2194 pl022->chipselects[i] = cs_gpio; in pl022_probe()
2197 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) in pl022_probe()
2198 dev_err(&adev->dev, in pl022_probe()
2202 dev_err(&adev->dev, in pl022_probe()
2210 * Supports mode 0-3, loopback, and active low CS. Transfers are in pl022_probe()
2213 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pl022_probe()
2214 if (pl022->vendor->extended_cr) in pl022_probe()
2215 master->mode_bits |= SPI_LSB_FIRST; in pl022_probe()
2217 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); in pl022_probe()
2223 pl022->phybase = adev->res.start; in pl022_probe()
2224 pl022->virtbase = devm_ioremap(dev, adev->res.start, in pl022_probe()
2225 resource_size(&adev->res)); in pl022_probe()
2226 if (pl022->virtbase == NULL) { in pl022_probe()
2227 status = -ENOMEM; in pl022_probe()
2230 dev_info(&adev->dev, "mapped registers from %pa to %p\n", in pl022_probe()
2231 &adev->res.start, pl022->virtbase); in pl022_probe()
2233 pl022->clk = devm_clk_get(&adev->dev, NULL); in pl022_probe()
2234 if (IS_ERR(pl022->clk)) { in pl022_probe()
2235 status = PTR_ERR(pl022->clk); in pl022_probe()
2236 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); in pl022_probe()
2240 status = clk_prepare_enable(pl022->clk); in pl022_probe()
2242 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); in pl022_probe()
2247 tasklet_init(&pl022->pump_transfers, pump_transfers, in pl022_probe()
2251 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), in pl022_probe()
2252 SSP_CR1(pl022->virtbase)); in pl022_probe()
2255 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, in pl022_probe()
2258 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); in pl022_probe()
2264 if (status == -EPROBE_DEFER) { in pl022_probe()
2271 platform_info->enable_dma = 1; in pl022_probe()
2272 else if (platform_info->enable_dma) { in pl022_probe()
2275 platform_info->enable_dma = 0; in pl022_probe()
2280 status = devm_spi_register_master(&adev->dev, master); in pl022_probe()
2282 dev_err(&adev->dev, in pl022_probe()
2283 "probe - problem registering spi master\n"); in pl022_probe()
2289 if (platform_info->autosuspend_delay > 0) { in pl022_probe()
2290 dev_info(&adev->dev, in pl022_probe()
2292 platform_info->autosuspend_delay); in pl022_probe()
2294 platform_info->autosuspend_delay); in pl022_probe()
2302 if (platform_info->enable_dma) in pl022_probe()
2305 clk_disable_unprepare(pl022->clk); in pl022_probe()
2329 pm_runtime_get_noresume(&adev->dev); in pl022_remove()
2332 if (pl022->master_info->enable_dma) in pl022_remove()
2335 clk_disable_unprepare(pl022->clk); in pl022_remove()
2337 tasklet_disable(&pl022->pump_transfers); in pl022_remove()
2347 ret = spi_master_suspend(pl022->master); in pl022_suspend()
2353 spi_master_resume(pl022->master); in pl022_suspend()
2373 ret = spi_master_resume(pl022->master); in pl022_resume()
2386 clk_disable_unprepare(pl022->clk); in pl022_runtime_suspend()
2397 clk_prepare_enable(pl022->clk); in pl022_runtime_resume()
2460 * ST Micro derivative, this has 32bit wide
2469 * ST-Ericsson derivative "PL023" (this is not
2495 .name = "ssp-pl022",