Lines Matching full:spi
19 #include <linux/spi/spi.h>
155 int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
188 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) in lantiq_ssc_readl() argument
190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
193 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, in lantiq_ssc_writel() argument
196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
199 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, in lantiq_ssc_maskl() argument
202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
206 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
209 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) in tx_fifo_level() argument
211 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
212 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); in tx_fifo_level()
217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) in rx_fifo_level() argument
219 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in rx_fifo_level()
220 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); in rx_fifo_level()
225 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) in tx_fifo_free() argument
227 return spi->tx_fifo_size - tx_fifo_level(spi); in tx_fifo_free()
230 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) in rx_fifo_reset() argument
232 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; in rx_fifo_reset()
235 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); in rx_fifo_reset()
238 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) in tx_fifo_reset() argument
243 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); in tx_fifo_reset()
246 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) in rx_fifo_flush() argument
248 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); in rx_fifo_flush()
251 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) in tx_fifo_flush() argument
253 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); in tx_fifo_flush()
256 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) in hw_enter_config_mode() argument
258 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); in hw_enter_config_mode()
261 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) in hw_enter_active_mode() argument
263 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); in hw_enter_active_mode()
266 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, in hw_setup_speed_hz() argument
272 * SPI module clock is derived from FPI bus clock dependent on in hw_setup_speed_hz()
279 spi_clk = clk_get_rate(spi->fpi_clk) / 2; in hw_setup_speed_hz()
289 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", in hw_setup_speed_hz()
292 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); in hw_setup_speed_hz()
295 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, in hw_setup_bits_per_word() argument
303 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); in hw_setup_bits_per_word()
306 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, in hw_setup_clock_mode() argument
312 * SPI mode mapping in CON register: in hw_setup_clock_mode()
341 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); in hw_setup_clock_mode()
344 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) in lantiq_ssc_hw_init() argument
346 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_hw_init()
352 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); in lantiq_ssc_hw_init()
355 hw_enter_config_mode(spi); in lantiq_ssc_hw_init()
358 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); in lantiq_ssc_hw_init()
361 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | in lantiq_ssc_hw_init()
365 /* Setup default SPI mode */ in lantiq_ssc_hw_init()
366 hw_setup_bits_per_word(spi, spi->bits_per_word); in lantiq_ssc_hw_init()
367 hw_setup_clock_mode(spi, SPI_MODE_0); in lantiq_ssc_hw_init()
370 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | in lantiq_ssc_hw_init()
375 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); in lantiq_ssc_hw_init()
376 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); in lantiq_ssc_hw_init()
379 rx_fifo_reset(spi); in lantiq_ssc_hw_init()
380 tx_fifo_reset(spi); in lantiq_ssc_hw_init()
383 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | in lantiq_ssc_hw_init()
390 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); in lantiq_ssc_setup() local
398 dev_dbg(spi->dev, "using internal chipselect %u\n", cs); in lantiq_ssc_setup()
400 if (cs < spi->base_cs) { in lantiq_ssc_setup()
401 dev_err(spi->dev, in lantiq_ssc_setup()
402 "chipselect %i too small (min %i)\n", cs, spi->base_cs); in lantiq_ssc_setup()
407 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); in lantiq_ssc_setup()
411 gpocon |= 1 << (cs - spi->base_cs); in lantiq_ssc_setup()
413 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); in lantiq_ssc_setup()
421 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); in lantiq_ssc_prepare_message() local
423 hw_enter_config_mode(spi); in lantiq_ssc_prepare_message()
424 hw_setup_clock_mode(spi, message->spi->mode); in lantiq_ssc_prepare_message()
425 hw_enter_active_mode(spi); in lantiq_ssc_prepare_message()
430 static void hw_setup_transfer(struct lantiq_ssc_spi *spi, in hw_setup_transfer() argument
437 if (bits_per_word != spi->bits_per_word || in hw_setup_transfer()
438 speed_hz != spi->speed_hz) { in hw_setup_transfer()
439 hw_enter_config_mode(spi); in hw_setup_transfer()
440 hw_setup_speed_hz(spi, speed_hz); in hw_setup_transfer()
441 hw_setup_bits_per_word(spi, bits_per_word); in hw_setup_transfer()
442 hw_enter_active_mode(spi); in hw_setup_transfer()
444 spi->speed_hz = speed_hz; in hw_setup_transfer()
445 spi->bits_per_word = bits_per_word; in hw_setup_transfer()
449 con = lantiq_ssc_readl(spi, LTQ_SPI_CON); in hw_setup_transfer()
460 lantiq_ssc_writel(spi, con, LTQ_SPI_CON); in hw_setup_transfer()
466 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); in lantiq_ssc_unprepare_message() local
468 flush_workqueue(spi->wq); in lantiq_ssc_unprepare_message()
471 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, in lantiq_ssc_unprepare_message()
477 static void tx_fifo_write(struct lantiq_ssc_spi *spi) in tx_fifo_write() argument
483 unsigned int tx_free = tx_fifo_free(spi); in tx_fifo_write()
485 spi->fdx_tx_level = 0; in tx_fifo_write()
486 while (spi->tx_todo && tx_free) { in tx_fifo_write()
487 switch (spi->bits_per_word) { in tx_fifo_write()
489 tx8 = spi->tx; in tx_fifo_write()
491 spi->tx_todo--; in tx_fifo_write()
492 spi->tx++; in tx_fifo_write()
495 tx16 = (u16 *) spi->tx; in tx_fifo_write()
497 spi->tx_todo -= 2; in tx_fifo_write()
498 spi->tx += 2; in tx_fifo_write()
501 tx32 = (u32 *) spi->tx; in tx_fifo_write()
503 spi->tx_todo -= 4; in tx_fifo_write()
504 spi->tx += 4; in tx_fifo_write()
512 lantiq_ssc_writel(spi, data, LTQ_SPI_TB); in tx_fifo_write()
514 spi->fdx_tx_level++; in tx_fifo_write()
518 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) in rx_fifo_read_full_duplex() argument
524 unsigned int rx_fill = rx_fifo_level(spi); in rx_fifo_read_full_duplex()
530 while (rx_fill != spi->fdx_tx_level) in rx_fifo_read_full_duplex()
531 rx_fill = rx_fifo_level(spi); in rx_fifo_read_full_duplex()
534 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); in rx_fifo_read_full_duplex()
536 switch (spi->bits_per_word) { in rx_fifo_read_full_duplex()
538 rx8 = spi->rx; in rx_fifo_read_full_duplex()
540 spi->rx_todo--; in rx_fifo_read_full_duplex()
541 spi->rx++; in rx_fifo_read_full_duplex()
544 rx16 = (u16 *) spi->rx; in rx_fifo_read_full_duplex()
546 spi->rx_todo -= 2; in rx_fifo_read_full_duplex()
547 spi->rx += 2; in rx_fifo_read_full_duplex()
550 rx32 = (u32 *) spi->rx; in rx_fifo_read_full_duplex()
552 spi->rx_todo -= 4; in rx_fifo_read_full_duplex()
553 spi->rx += 4; in rx_fifo_read_full_duplex()
564 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) in rx_fifo_read_half_duplex() argument
569 unsigned int rx_fill = rx_fifo_level(spi); in rx_fifo_read_half_duplex()
579 if (spi->rx_todo < 4) { in rx_fifo_read_half_duplex()
580 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & in rx_fifo_read_half_duplex()
582 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); in rx_fifo_read_half_duplex()
585 rx8 = spi->rx; in rx_fifo_read_half_duplex()
591 spi->rx_todo--; in rx_fifo_read_half_duplex()
592 spi->rx++; in rx_fifo_read_half_duplex()
595 data = lantiq_ssc_readl(spi, LTQ_SPI_RB); in rx_fifo_read_half_duplex()
596 rx32 = (u32 *) spi->rx; in rx_fifo_read_half_duplex()
599 spi->rx_todo -= 4; in rx_fifo_read_half_duplex()
600 spi->rx += 4; in rx_fifo_read_half_duplex()
606 static void rx_request(struct lantiq_ssc_spi *spi) in rx_request() argument
615 rxreq = spi->rx_todo; in rx_request()
616 rxreq_max = spi->rx_fifo_size * 4; in rx_request()
620 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); in rx_request()
625 struct lantiq_ssc_spi *spi = data; in lantiq_ssc_xmit_interrupt() local
626 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_xmit_interrupt()
627 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in lantiq_ssc_xmit_interrupt()
629 spin_lock(&spi->lock); in lantiq_ssc_xmit_interrupt()
631 lantiq_ssc_writel(spi, val, hwcfg->irncr); in lantiq_ssc_xmit_interrupt()
633 if (spi->tx) { in lantiq_ssc_xmit_interrupt()
634 if (spi->rx && spi->rx_todo) in lantiq_ssc_xmit_interrupt()
635 rx_fifo_read_full_duplex(spi); in lantiq_ssc_xmit_interrupt()
637 if (spi->tx_todo) in lantiq_ssc_xmit_interrupt()
638 tx_fifo_write(spi); in lantiq_ssc_xmit_interrupt()
639 else if (!tx_fifo_level(spi)) in lantiq_ssc_xmit_interrupt()
641 } else if (spi->rx) { in lantiq_ssc_xmit_interrupt()
642 if (spi->rx_todo) { in lantiq_ssc_xmit_interrupt()
643 rx_fifo_read_half_duplex(spi); in lantiq_ssc_xmit_interrupt()
645 if (spi->rx_todo) in lantiq_ssc_xmit_interrupt()
646 rx_request(spi); in lantiq_ssc_xmit_interrupt()
654 spin_unlock(&spi->lock); in lantiq_ssc_xmit_interrupt()
658 queue_work(spi->wq, &spi->work); in lantiq_ssc_xmit_interrupt()
659 spin_unlock(&spi->lock); in lantiq_ssc_xmit_interrupt()
666 struct lantiq_ssc_spi *spi = data; in lantiq_ssc_err_interrupt() local
667 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in lantiq_ssc_err_interrupt()
668 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); in lantiq_ssc_err_interrupt()
669 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in lantiq_ssc_err_interrupt()
674 spin_lock(&spi->lock); in lantiq_ssc_err_interrupt()
676 lantiq_ssc_writel(spi, val, hwcfg->irncr); in lantiq_ssc_err_interrupt()
679 dev_err(spi->dev, "receive underflow error\n"); in lantiq_ssc_err_interrupt()
681 dev_err(spi->dev, "transmit underflow error\n"); in lantiq_ssc_err_interrupt()
683 dev_err(spi->dev, "abort error\n"); in lantiq_ssc_err_interrupt()
685 dev_err(spi->dev, "receive overflow error\n"); in lantiq_ssc_err_interrupt()
687 dev_err(spi->dev, "transmit overflow error\n"); in lantiq_ssc_err_interrupt()
689 dev_err(spi->dev, "mode error\n"); in lantiq_ssc_err_interrupt()
692 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); in lantiq_ssc_err_interrupt()
695 if (spi->master->cur_msg) in lantiq_ssc_err_interrupt()
696 spi->master->cur_msg->status = -EIO; in lantiq_ssc_err_interrupt()
697 queue_work(spi->wq, &spi->work); in lantiq_ssc_err_interrupt()
698 spin_unlock(&spi->lock); in lantiq_ssc_err_interrupt()
705 struct lantiq_ssc_spi *spi = data; in intel_lgm_ssc_isr() local
706 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in intel_lgm_ssc_isr()
707 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); in intel_lgm_ssc_isr()
721 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev, in transfer_start() argument
726 spin_lock_irqsave(&spi->lock, flags); in transfer_start()
728 spi->tx = t->tx_buf; in transfer_start()
729 spi->rx = t->rx_buf; in transfer_start()
732 spi->tx_todo = t->len; in transfer_start()
735 tx_fifo_write(spi); in transfer_start()
738 if (spi->rx) { in transfer_start()
739 spi->rx_todo = t->len; in transfer_start()
742 if (!spi->tx) in transfer_start()
743 rx_request(spi); in transfer_start()
746 spin_unlock_irqrestore(&spi->lock, flags); in transfer_start()
760 struct lantiq_ssc_spi *spi; in lantiq_ssc_bussy_work() local
764 spi = container_of(work, typeof(*spi), work); in lantiq_ssc_bussy_work()
766 do_div(timeout, spi->speed_hz); in lantiq_ssc_bussy_work()
771 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); in lantiq_ssc_bussy_work()
774 spi_finalize_current_transfer(spi->master); in lantiq_ssc_bussy_work()
781 if (spi->master->cur_msg) in lantiq_ssc_bussy_work()
782 spi->master->cur_msg->status = -EIO; in lantiq_ssc_bussy_work()
783 spi_finalize_current_transfer(spi->master); in lantiq_ssc_bussy_work()
789 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); in lantiq_ssc_handle_err() local
792 rx_fifo_flush(spi); in lantiq_ssc_handle_err()
793 tx_fifo_flush(spi); in lantiq_ssc_handle_err()
798 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master); in lantiq_ssc_set_cs() local
803 fgpo = (1 << (cs - spi->base_cs)); in lantiq_ssc_set_cs()
805 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); in lantiq_ssc_set_cs()
807 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); in lantiq_ssc_set_cs()
814 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); in lantiq_ssc_transfer_one() local
816 hw_setup_transfer(spi, spidev, t); in lantiq_ssc_transfer_one()
818 return transfer_start(spi, spidev, t); in lantiq_ssc_transfer_one()
821 static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi) in intel_lgm_cfg_irq() argument
829 return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi); in intel_lgm_cfg_irq()
832 static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi) in lantiq_cfg_irq() argument
841 0, LTQ_SPI_RX_IRQ_NAME, spi); in lantiq_cfg_irq()
850 0, LTQ_SPI_TX_IRQ_NAME, spi); in lantiq_cfg_irq()
860 0, LTQ_SPI_ERR_IRQ_NAME, spi); in lantiq_cfg_irq()
895 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
896 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
897 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
898 { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
907 struct lantiq_ssc_spi *spi; in lantiq_ssc_probe() local
925 spi = spi_master_get_devdata(master); in lantiq_ssc_probe()
926 spi->master = master; in lantiq_ssc_probe()
927 spi->dev = dev; in lantiq_ssc_probe()
928 spi->hwcfg = hwcfg; in lantiq_ssc_probe()
929 platform_set_drvdata(pdev, spi); in lantiq_ssc_probe()
930 spi->regbase = devm_platform_ioremap_resource(pdev, 0); in lantiq_ssc_probe()
931 if (IS_ERR(spi->regbase)) { in lantiq_ssc_probe()
932 err = PTR_ERR(spi->regbase); in lantiq_ssc_probe()
936 err = hwcfg->cfg_irq(pdev, spi); in lantiq_ssc_probe()
940 spi->spi_clk = devm_clk_get(dev, "gate"); in lantiq_ssc_probe()
941 if (IS_ERR(spi->spi_clk)) { in lantiq_ssc_probe()
942 err = PTR_ERR(spi->spi_clk); in lantiq_ssc_probe()
945 err = clk_prepare_enable(spi->spi_clk); in lantiq_ssc_probe()
954 spi->fpi_clk = clk_get_fpi(); in lantiq_ssc_probe()
956 spi->fpi_clk = clk_get(dev, "freq"); in lantiq_ssc_probe()
958 if (IS_ERR(spi->fpi_clk)) { in lantiq_ssc_probe()
959 err = PTR_ERR(spi->fpi_clk); in lantiq_ssc_probe()
966 spi->base_cs = 1; in lantiq_ssc_probe()
967 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs); in lantiq_ssc_probe()
969 spin_lock_init(&spi->lock); in lantiq_ssc_probe()
970 spi->bits_per_word = 8; in lantiq_ssc_probe()
971 spi->speed_hz = 0; in lantiq_ssc_probe()
987 spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM); in lantiq_ssc_probe()
988 if (!spi->wq) { in lantiq_ssc_probe()
992 INIT_WORK(&spi->work, lantiq_ssc_bussy_work); in lantiq_ssc_probe()
994 id = lantiq_ssc_readl(spi, LTQ_SPI_ID); in lantiq_ssc_probe()
995 spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask; in lantiq_ssc_probe()
996 spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask; in lantiq_ssc_probe()
1000 lantiq_ssc_hw_init(spi); in lantiq_ssc_probe()
1003 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n", in lantiq_ssc_probe()
1004 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); in lantiq_ssc_probe()
1015 destroy_workqueue(spi->wq); in lantiq_ssc_probe()
1017 clk_put(spi->fpi_clk); in lantiq_ssc_probe()
1019 clk_disable_unprepare(spi->spi_clk); in lantiq_ssc_probe()
1028 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); in lantiq_ssc_remove() local
1030 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); in lantiq_ssc_remove()
1031 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); in lantiq_ssc_remove()
1032 rx_fifo_flush(spi); in lantiq_ssc_remove()
1033 tx_fifo_flush(spi); in lantiq_ssc_remove()
1034 hw_enter_config_mode(spi); in lantiq_ssc_remove()
1036 destroy_workqueue(spi->wq); in lantiq_ssc_remove()
1037 clk_disable_unprepare(spi->spi_clk); in lantiq_ssc_remove()
1038 clk_put(spi->fpi_clk); in lantiq_ssc_remove()
1047 .name = "spi-lantiq-ssc",
1053 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
1057 MODULE_ALIAS("platform:spi-lantiq-ssc");