12 #include <linux/qcom-geni-se.h>
16 /* SPI SE specific registers and respective register fields */
67 	struct geni_se se;  member
97 	ret = geni_se_clk_freq_match(&mas->se,  in get_spi_clk_cfg()
125 	struct geni_se *se = &mas->se;  in handle_fifo_timeout()  local
129 	writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in handle_fifo_timeout()
131 	geni_se_cancel_m_cmd(se);  in handle_fifo_timeout()
140 	geni_se_abort_m_cmd(se);  in handle_fifo_timeout()
152 	struct geni_se *se = &mas->se;  in spi_geni_set_cs()  local
167 		geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);  in spi_geni_set_cs()
169 		geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);  in spi_geni_set_cs()
184 	struct geni_se *se = &mas->se;  in spi_setup_word_len()  local
195 	geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,  in spi_setup_word_len()
198 	writel(word_len, se->base + SE_SPI_WORD_LEN);  in spi_setup_word_len()
205 	struct geni_se *se = &mas->se;  in geni_spi_set_clock_and_bw()  local
228 	writel(clk_sel, se->base + SE_GENI_CLK_SEL);  in geni_spi_set_clock_and_bw()
229 	writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);  in geni_spi_set_clock_and_bw()
232 	se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);  in geni_spi_set_clock_and_bw()
233 	ret = geni_icc_set_bw(se);  in geni_spi_set_clock_and_bw()
244 	struct geni_se *se = &mas->se;  in setup_fifo_params()  local
265 		writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);  in setup_fifo_params()
266 		writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);  in setup_fifo_params()
267 		writel(cpha, se->base + SE_SPI_CPHA);  in setup_fifo_params()
268 		writel(cpol, se->base + SE_SPI_CPOL);  in setup_fifo_params()
269 		writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);  in setup_fifo_params()
291 	struct geni_se *se = &mas->se;  in spi_geni_init()  local
297 	proto = geni_se_read_proto(se);  in spi_geni_init()
303 	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);  in spi_geni_init()
306 	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);  in spi_geni_init()
312 	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);  in spi_geni_init()
315 	ver = geni_se_get_qup_hw_version(se);  in spi_geni_init()
324 	geni_se_select_mode(se, GENI_SE_FIFO);  in spi_geni_init()
327 	spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
329 	writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
351 	struct geni_se *se = &mas->se;  in geni_spi_handle_tx()  local
371 		iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);  in geni_spi_handle_tx()
375 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
383 	struct geni_se *se = &mas->se;  in geni_spi_handle_rx()  local
391 	rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);  in geni_spi_handle_rx()
410 		ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);  in geni_spi_handle_rx()
423 	struct geni_se *se = &mas->se;  in setup_fifo_xfer()  local
464 		writel(len, se->base + SE_SPI_TX_TRANS_LEN);  in setup_fifo_xfer()
469 		writel(len, se->base + SE_SPI_RX_TRANS_LEN);  in setup_fifo_xfer()
478 	geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);  in setup_fifo_xfer()
482 	 * setting up GENI SE engine, as driver starts data transfer  in setup_fifo_xfer()
487 			writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);  in setup_fifo_xfer()
510 	struct geni_se *se = &mas->se;  in geni_spi_isr()  local
513 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in geni_spi_isr()
548 				writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_isr()
578 	writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_spi_isr()
602 	clk = devm_clk_get(dev, "se");  in spi_geni_probe()
614 	mas->se.dev = dev;  in spi_geni_probe()
615 	mas->se.wrapper = dev_get_drvdata(dev->parent);  in spi_geni_probe()
616 	mas->se.base = base;  in spi_geni_probe()
617 	mas->se.clk = clk;  in spi_geni_probe()
618 	mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");  in spi_geni_probe()
619 	if (IS_ERR(mas->se.opp_table))  in spi_geni_probe()
620 		return PTR_ERR(mas->se.opp_table);  in spi_geni_probe()
648 	ret = geni_icc_get(&mas->se, NULL);  in spi_geni_probe()
652 	mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);  in spi_geni_probe()
653 	mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in spi_geni_probe()
655 	ret = geni_icc_set_bw(&mas->se);  in spi_geni_probe()
679 	dev_pm_opp_put_clkname(mas->se.opp_table);  in spi_geni_probe()
694 	dev_pm_opp_put_clkname(mas->se.opp_table);  in spi_geni_remove()
707 	ret = geni_se_resources_off(&mas->se);  in spi_geni_runtime_suspend()
711 	return geni_icc_disable(&mas->se);  in spi_geni_runtime_suspend()
720 	ret = geni_icc_enable(&mas->se);  in spi_geni_runtime_resume()
724 	ret = geni_se_resources_on(&mas->se);  in spi_geni_runtime_resume()