Lines Matching +full:geni +full:- +full:se +full:- +full:qup
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
12 #include <linux/qcom-geni-se.h>
16 /* SPI SE specific registers and respective register fields */
67 struct geni_se se; member
97 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
98 speed_hz * mas->oversampling, in get_spi_clk_cfg()
101 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
106 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
107 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
109 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
111 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
113 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
115 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
125 struct geni_se *se = &mas->se; in handle_fifo_timeout() local
127 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
128 reinit_completion(&mas->cancel_done); in handle_fifo_timeout()
129 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
130 mas->cur_xfer = NULL; in handle_fifo_timeout()
131 geni_se_cancel_m_cmd(se); in handle_fifo_timeout()
132 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
134 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_fifo_timeout()
138 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
139 reinit_completion(&mas->abort_done); in handle_fifo_timeout()
140 geni_se_abort_m_cmd(se); in handle_fifo_timeout()
141 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
143 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_fifo_timeout()
145 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_fifo_timeout()
150 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in spi_geni_set_cs()
151 struct spi_master *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs()
152 struct geni_se *se = &mas->se; in spi_geni_set_cs() local
155 if (!(slv->mode & SPI_CS_HIGH)) in spi_geni_set_cs()
158 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
161 mas->cs_flag = set_flag; in spi_geni_set_cs()
163 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
164 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
165 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
167 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); in spi_geni_set_cs()
169 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); in spi_geni_set_cs()
170 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
172 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
176 pm_runtime_put(mas->dev); in spi_geni_set_cs()
184 struct geni_se *se = &mas->se; in spi_setup_word_len() local
191 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
192 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
195 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
197 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; in spi_setup_word_len()
198 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
205 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw() local
208 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
213 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
224 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
228 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
229 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
232 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
233 ret = geni_icc_set_bw(se); in geni_spi_set_clock_and_bw()
244 struct geni_se *se = &mas->se; in setup_fifo_params() local
248 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
249 if (spi_slv->mode & SPI_LOOP) in setup_fifo_params()
252 if (spi_slv->mode & SPI_CPOL) in setup_fifo_params()
255 if (spi_slv->mode & SPI_CPHA) in setup_fifo_params()
258 if (spi_slv->mode & SPI_CS_HIGH) in setup_fifo_params()
259 demux_output_inv = BIT(spi_slv->chip_select); in setup_fifo_params()
261 demux_sel = spi_slv->chip_select; in setup_fifo_params()
262 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
264 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
265 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
266 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
267 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
268 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
269 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
271 mas->last_mode = spi_slv->mode; in setup_fifo_params()
274 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
283 ret = setup_fifo_params(spi_msg->spi, spi); in spi_geni_prepare_message()
285 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
291 struct geni_se *se = &mas->se; in spi_geni_init() local
295 pm_runtime_get_sync(mas->dev); in spi_geni_init()
297 proto = geni_se_read_proto(se); in spi_geni_init()
299 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
300 pm_runtime_put(mas->dev); in spi_geni_init()
301 return -ENXIO; in spi_geni_init()
303 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
306 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
310 * RX FIFO RFR level to fifo_depth-2. in spi_geni_init()
312 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
314 mas->tx_wm = 1; in spi_geni_init()
315 ver = geni_se_get_qup_hw_version(se); in spi_geni_init()
320 mas->oversampling = 2; in spi_geni_init()
322 mas->oversampling = 1; in spi_geni_init()
324 geni_se_select_mode(se, GENI_SE_FIFO); in spi_geni_init()
327 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
329 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
331 pm_runtime_put(mas->dev); in spi_geni_init()
342 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
343 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
346 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
351 struct geni_se *se = &mas->se; in geni_spi_handle_tx() local
357 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
358 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
359 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
361 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
368 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); in geni_spi_handle_tx()
371 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
373 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
374 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
375 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
383 struct geni_se *se = &mas->se; in geni_spi_handle_rx() local
391 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
397 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; in geni_spi_handle_rx()
399 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
400 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
402 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
409 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); in geni_spi_handle_rx()
410 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
414 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
423 struct geni_se *se = &mas->se; in setup_fifo_xfer() local
438 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
439 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
441 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_fifo_xfer()
442 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_fifo_xfer()
443 mas->cur_bits_per_word = xfer->bits_per_word; in setup_fifo_xfer()
447 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_fifo_xfer()
451 mas->tx_rem_bytes = 0; in setup_fifo_xfer()
452 mas->rx_rem_bytes = 0; in setup_fifo_xfer()
454 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in setup_fifo_xfer()
455 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in setup_fifo_xfer()
457 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in setup_fifo_xfer()
460 mas->cur_xfer = xfer; in setup_fifo_xfer()
461 if (xfer->tx_buf) { in setup_fifo_xfer()
463 mas->tx_rem_bytes = xfer->len; in setup_fifo_xfer()
464 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_fifo_xfer()
467 if (xfer->rx_buf) { in setup_fifo_xfer()
469 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_fifo_xfer()
470 mas->rx_rem_bytes = xfer->len; in setup_fifo_xfer()
477 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
478 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); in setup_fifo_xfer()
482 * setting up GENI SE engine, as driver starts data transfer in setup_fifo_xfer()
487 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_fifo_xfer()
489 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
499 if (!xfer->len) in spi_geni_transfer_one()
502 setup_fifo_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
510 struct geni_se *se = &mas->se; in geni_spi_isr() local
513 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
520 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
522 spin_lock(&mas->lock); in geni_spi_isr()
531 if (mas->cur_xfer) { in geni_spi_isr()
533 mas->cur_xfer = NULL; in geni_spi_isr()
547 if (mas->tx_rem_bytes) { in geni_spi_isr()
548 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
549 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
550 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
552 if (mas->rx_rem_bytes) in geni_spi_isr()
553 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
554 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
556 complete(&mas->cs_done); in geni_spi_isr()
561 complete(&mas->cancel_done); in geni_spi_isr()
563 complete(&mas->abort_done); in geni_spi_isr()
568 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and in geni_spi_isr()
573 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear in geni_spi_isr()
576 * since they'll re-assert if they're still happening. in geni_spi_isr()
578 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
580 spin_unlock(&mas->lock); in geni_spi_isr()
592 struct device *dev = &pdev->dev; in spi_geni_probe()
602 clk = devm_clk_get(dev, "se"); in spi_geni_probe()
608 return -ENOMEM; in spi_geni_probe()
612 mas->irq = irq; in spi_geni_probe()
613 mas->dev = dev; in spi_geni_probe()
614 mas->se.dev = dev; in spi_geni_probe()
615 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
616 mas->se.base = base; in spi_geni_probe()
617 mas->se.clk = clk; in spi_geni_probe()
618 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
619 if (IS_ERR(mas->se.opp_table)) in spi_geni_probe()
620 return PTR_ERR(mas->se.opp_table); in spi_geni_probe()
622 ret = dev_pm_opp_of_add_table(&pdev->dev); in spi_geni_probe()
623 if (ret && ret != -ENODEV) { in spi_geni_probe()
624 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in spi_geni_probe()
628 spi->bus_num = -1; in spi_geni_probe()
629 spi->dev.of_node = dev->of_node; in spi_geni_probe()
630 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; in spi_geni_probe()
631 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_geni_probe()
632 spi->num_chipselect = 4; in spi_geni_probe()
633 spi->max_speed_hz = 50000000; in spi_geni_probe()
634 spi->prepare_message = spi_geni_prepare_message; in spi_geni_probe()
635 spi->transfer_one = spi_geni_transfer_one; in spi_geni_probe()
636 spi->auto_runtime_pm = true; in spi_geni_probe()
637 spi->handle_err = handle_fifo_timeout; in spi_geni_probe()
638 spi->set_cs = spi_geni_set_cs; in spi_geni_probe()
640 init_completion(&mas->cs_done); in spi_geni_probe()
641 init_completion(&mas->cancel_done); in spi_geni_probe()
642 init_completion(&mas->abort_done); in spi_geni_probe()
643 spin_lock_init(&mas->lock); in spi_geni_probe()
644 pm_runtime_use_autosuspend(&pdev->dev); in spi_geni_probe()
645 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); in spi_geni_probe()
648 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
652 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
653 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
655 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
663 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
673 free_irq(mas->irq, spi); in spi_geni_probe()
677 dev_pm_opp_of_remove_table(&pdev->dev); in spi_geni_probe()
679 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_probe()
691 free_irq(mas->irq, spi); in spi_geni_remove()
692 pm_runtime_disable(&pdev->dev); in spi_geni_remove()
693 dev_pm_opp_of_remove_table(&pdev->dev); in spi_geni_remove()
694 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_remove()
707 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
711 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
720 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
724 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
728 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()
770 { .compatible = "qcom,geni-spi" },
786 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");