Lines Matching +full:rx +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-dw.h>
18 #include "spi-dw.h"
29 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
32 chan->private = s; in dw_spi_dma_chan_filter()
42 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
44 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
50 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
51 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
53 ret = dma_get_slave_caps(dws->txchan, &caps); in dw_spi_dma_maxburst_init()
60 * Having a Rx DMA channel serviced with higher priority than a Tx DMA in dw_spi_dma_maxburst_init()
61 * channel might not be enough to provide a well balanced DMA-based in dw_spi_dma_maxburst_init()
63 * channel is occasionally handled faster than the Rx DMA channel. in dw_spi_dma_maxburst_init()
64 * That in its turn will eventually cause the SPI Rx FIFO overflow if in dw_spi_dma_maxburst_init()
65 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's in dw_spi_dma_maxburst_init()
66 * cleared by the Rx DMA channel. In order to fix the problem the Tx in dw_spi_dma_maxburst_init()
70 dws->txburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
71 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); in dw_spi_dma_maxburst_init()
76 struct dma_slave_caps tx = {0}, rx = {0}; in dw_spi_dma_sg_burst_init() local
78 dma_get_slave_caps(dws->txchan, &tx); in dw_spi_dma_sg_burst_init()
79 dma_get_slave_caps(dws->rxchan, &rx); in dw_spi_dma_sg_burst_init()
81 if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0) in dw_spi_dma_sg_burst_init()
82 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); in dw_spi_dma_sg_burst_init()
84 dws->dma_sg_burst = tx.max_sg_burst; in dw_spi_dma_sg_burst_init()
85 else if (rx.max_sg_burst > 0) in dw_spi_dma_sg_burst_init()
86 dws->dma_sg_burst = rx.max_sg_burst; in dw_spi_dma_sg_burst_init()
88 dws->dma_sg_burst = 0; in dw_spi_dma_sg_burst_init()
94 struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx; in dw_spi_dma_init_mfld() local
104 return -ENODEV; in dw_spi_dma_init_mfld()
109 /* 1. Init rx channel */ in dw_spi_dma_init_mfld()
110 rx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
111 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx); in dw_spi_dma_init_mfld()
112 if (!dws->rxchan) in dw_spi_dma_init_mfld()
116 tx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
117 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx); in dw_spi_dma_init_mfld()
118 if (!dws->txchan) in dw_spi_dma_init_mfld()
121 dws->master->dma_rx = dws->rxchan; in dw_spi_dma_init_mfld()
122 dws->master->dma_tx = dws->txchan; in dw_spi_dma_init_mfld()
124 init_completion(&dws->dma_completion); in dw_spi_dma_init_mfld()
133 dma_release_channel(dws->rxchan); in dw_spi_dma_init_mfld()
134 dws->rxchan = NULL; in dw_spi_dma_init_mfld()
136 return -EBUSY; in dw_spi_dma_init_mfld()
141 dws->rxchan = dma_request_slave_channel(dev, "rx"); in dw_spi_dma_init_generic()
142 if (!dws->rxchan) in dw_spi_dma_init_generic()
143 return -ENODEV; in dw_spi_dma_init_generic()
145 dws->txchan = dma_request_slave_channel(dev, "tx"); in dw_spi_dma_init_generic()
146 if (!dws->txchan) { in dw_spi_dma_init_generic()
147 dma_release_channel(dws->rxchan); in dw_spi_dma_init_generic()
148 dws->rxchan = NULL; in dw_spi_dma_init_generic()
149 return -ENODEV; in dw_spi_dma_init_generic()
152 dws->master->dma_rx = dws->rxchan; in dw_spi_dma_init_generic()
153 dws->master->dma_tx = dws->txchan; in dw_spi_dma_init_generic()
155 init_completion(&dws->dma_completion); in dw_spi_dma_init_generic()
166 if (dws->txchan) { in dw_spi_dma_exit()
167 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_exit()
168 dma_release_channel(dws->txchan); in dw_spi_dma_exit()
171 if (dws->rxchan) { in dw_spi_dma_exit()
172 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_exit()
173 dma_release_channel(dws->rxchan); in dw_spi_dma_exit()
181 complete(&dws->dma_completion); in dw_spi_dma_transfer_handler()
191 return xfer->len > dws->fifo_len; in dw_spi_can_dma()
215 ms = wait_for_completion_timeout(&dws->dma_completion, in dw_spi_dma_wait()
219 dev_err(&dws->master->cur_msg->spi->dev, in dw_spi_dma_wait()
221 return -ETIMEDOUT; in dw_spi_dma_wait()
236 struct spi_delay delay; in dw_spi_dma_wait_tx_done() local
240 delay.unit = SPI_DELAY_UNIT_SCK; in dw_spi_dma_wait_tx_done()
241 delay.value = nents * dws->n_bytes * BITS_PER_BYTE; in dw_spi_dma_wait_tx_done()
243 while (dw_spi_dma_tx_busy(dws) && retry--) in dw_spi_dma_wait_tx_done()
244 spi_delay_exec(&delay, xfer); in dw_spi_dma_wait_tx_done()
247 dev_err(&dws->master->dev, "Tx hanged up\n"); in dw_spi_dma_wait_tx_done()
248 return -EIO; in dw_spi_dma_wait_tx_done()
255 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
262 clear_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_tx_done()
263 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_tx_done()
266 complete(&dws->dma_completion); in dw_spi_dma_tx_done()
275 txconf.dst_addr = dws->dma_addr; in dw_spi_dma_config_tx()
276 txconf.dst_maxburst = dws->txburst; in dw_spi_dma_config_tx()
278 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_tx()
281 return dmaengine_slave_config(dws->txchan, &txconf); in dw_spi_dma_config_tx()
291 txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents, in dw_spi_dma_submit_tx()
295 return -ENOMEM; in dw_spi_dma_submit_tx()
297 txdesc->callback = dw_spi_dma_tx_done; in dw_spi_dma_submit_tx()
298 txdesc->callback_param = dws; in dw_spi_dma_submit_tx()
303 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_submit_tx()
307 set_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_tx()
320 struct spi_delay delay; in dw_spi_dma_wait_rx_done() local
321 unsigned long ns, us; in dw_spi_dma_wait_rx_done() local
328 * number of data entries left in the Rx FIFO, times a number of clock in dw_spi_dma_wait_rx_done()
334 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; in dw_spi_dma_wait_rx_done()
335 if (ns <= NSEC_PER_USEC) { in dw_spi_dma_wait_rx_done()
336 delay.unit = SPI_DELAY_UNIT_NSECS; in dw_spi_dma_wait_rx_done()
337 delay.value = ns; in dw_spi_dma_wait_rx_done()
339 us = DIV_ROUND_UP(ns, NSEC_PER_USEC); in dw_spi_dma_wait_rx_done()
340 delay.unit = SPI_DELAY_UNIT_USECS; in dw_spi_dma_wait_rx_done()
341 delay.value = clamp_val(us, 0, USHRT_MAX); in dw_spi_dma_wait_rx_done()
344 while (dw_spi_dma_rx_busy(dws) && retry--) in dw_spi_dma_wait_rx_done()
345 spi_delay_exec(&delay, NULL); in dw_spi_dma_wait_rx_done()
348 dev_err(&dws->master->dev, "Rx hanged up\n"); in dw_spi_dma_wait_rx_done()
349 return -EIO; in dw_spi_dma_wait_rx_done()
356 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
363 clear_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_rx_done()
364 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_rx_done()
367 complete(&dws->dma_completion); in dw_spi_dma_rx_done()
376 rxconf.src_addr = dws->dma_addr; in dw_spi_dma_config_rx()
377 rxconf.src_maxburst = dws->rxburst; in dw_spi_dma_config_rx()
379 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_rx()
382 return dmaengine_slave_config(dws->rxchan, &rxconf); in dw_spi_dma_config_rx()
392 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents, in dw_spi_dma_submit_rx()
396 return -ENOMEM; in dw_spi_dma_submit_rx()
398 rxdesc->callback = dw_spi_dma_rx_done; in dw_spi_dma_submit_rx()
399 rxdesc->callback_param = dws; in dw_spi_dma_submit_rx()
404 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_submit_rx()
408 set_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_rx()
418 if (!xfer->tx_buf) in dw_spi_dma_setup()
419 return -EINVAL; in dw_spi_dma_setup()
426 if (xfer->rx_buf) { in dw_spi_dma_setup()
434 if (xfer->rx_buf) in dw_spi_dma_setup()
440 if (xfer->rx_buf) in dw_spi_dma_setup()
444 reinit_completion(&dws->dma_completion); in dw_spi_dma_setup()
446 dws->transfer_handler = dw_spi_dma_transfer_handler; in dw_spi_dma_setup()
457 ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); in dw_spi_dma_transfer_all()
461 /* Submit the DMA Rx transfer if required */ in dw_spi_dma_transfer_all()
462 if (xfer->rx_buf) { in dw_spi_dma_transfer_all()
463 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl, in dw_spi_dma_transfer_all()
464 xfer->rx_sg.nents); in dw_spi_dma_transfer_all()
468 /* rx must be started before tx due to spi instinct */ in dw_spi_dma_transfer_all()
469 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_all()
472 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_all()
474 ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz); in dw_spi_dma_transfer_all()
485 * likely work that around by performing the IRQ-based SG list entries
487 * recharged and re-executed before the Rx DMA channel. Due to
488 * non-deterministic IRQ-handler execution latency the DMA Tx channel will
489 * start pushing data to the SPI bus before the Rx DMA channel is even
491 * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
492 * the DMA Rx channel being recharged and re-executed will eventually be
496 * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
497 * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
499 * (though total length should match) let's virtually split the SG-lists to the
500 * set of DMA transfers, which length is a minimum of the ordered SG-entries
501 * lengths. An ASCII-sketch of the implemented algo is following:
502 * xfer->len
525 for (base = 0, len = 0; base < xfer->len; base += len) { in dw_spi_dma_transfer_one()
528 tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg); in dw_spi_dma_transfer_one()
533 /* Fetch next Rx DMA data chunk */ in dw_spi_dma_transfer_one()
535 rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg); in dw_spi_dma_transfer_one()
550 /* Submit DMA Rx transfer */ in dw_spi_dma_transfer_one()
555 /* Rx must be started before Tx due to SPI instinct */ in dw_spi_dma_transfer_one()
556 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_one()
558 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_one()
564 * data left in the Tx/Rx FIFOs. in dw_spi_dma_transfer_one()
566 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); in dw_spi_dma_transfer_one()
570 reinit_completion(&dws->dma_completion); in dw_spi_dma_transfer_one()
574 tx_len -= len; in dw_spi_dma_transfer_one()
575 rx_len -= len; in dw_spi_dma_transfer_one()
588 nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents); in dw_spi_dma_transfer()
591 * Execute normal DMA-based transfer (which submits the Rx and Tx SG in dw_spi_dma_transfer()
594 * Tx-only SPI transfer is requested, or the DMA engine is capable to in dw_spi_dma_transfer()
597 if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst) in dw_spi_dma_transfer()
604 if (dws->master->cur_msg->status == -EINPROGRESS) { in dw_spi_dma_transfer()
610 if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS) in dw_spi_dma_transfer()
618 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
619 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_stop()
620 clear_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
622 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
623 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_stop()
624 clear_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
639 dws->dma_ops = &dw_spi_dma_mfld_ops; in dw_spi_dma_setup_mfld()
654 dws->dma_ops = &dw_spi_dma_generic_ops; in dw_spi_dma_setup_generic()