224 #define spi_readl(port, reg) \  macro
354 		mr = spi_readl(as, MR);  in cs_activate()
364 			csr = spi_readl(as, CSR0 + 4 * i);  in cs_activate()
370 		mr = spi_readl(as, MR);  in cs_activate()
393 	mr = spi_readl(as, MR);  in cs_deactivate()
597 	spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
598 	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {  in atmel_spi_next_xfer_single()
599 		spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
641 	while (spi_readl(as, FLR))  in atmel_spi_next_xfer_fifo()
645 	fifomr = spi_readl(as, FMR);  in atmel_spi_next_xfer_fifo()
649 	(void)spi_readl(as, SR);  in atmel_spi_next_xfer_fifo()
857 	csr = spi_readl(as, CSR0 + 4 * chip_select);  in atmel_spi_set_xfer_speed()
995 		*rxp16 = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
998 		*rxp = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
1013 	u32 fifolr = spi_readl(as, FLR);  in atmel_spi_pump_fifo_data()
1036 		rd = spi_readl(as, RDR);  in atmel_spi_pump_fifo_data()
1073 	imr = spi_readl(as, IMR);  in atmel_spi_pio_interrupt()
1074 	status = spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1095 		spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1130 	imr = spi_readl(as, IMR);  in atmel_spi_pdc_interrupt()
1131 	status = spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1142 		spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1363 				spi_readl(as, TCR), spi_readl(as, RCR));  in atmel_spi_one_transfer()
1374 				if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))  in atmel_spi_one_transfer()
1379 			while (spi_readl(as, SR) & SPI_BIT(RDRF))  in atmel_spi_one_transfer()
1380 				spi_readl(as, RDR);  in atmel_spi_one_transfer()
1383 			spi_readl(as, SR);  in atmel_spi_one_transfer()
1487 	return spi_readl(as, VERSION) & 0x00000fff;  in atmel_get_version()
1707 	spi_readl(as, SR);  in atmel_spi_remove()