Lines Matching refs:reg_read
109 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); member
245 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val); in qcom_swrm_cmd_fifo_rd_cmd()
262 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
279 ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts); in qcom_swrm_irq_handler()
282 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
327 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
387 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
435 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
733 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
807 ctrl->reg_read = qcom_swrm_ahb_reg_read;
813 ctrl->reg_read = qcom_swrm_cpu_reg_read;
853 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
865 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);