22 #define SWRM_COMP_HW_VERSION					0x00
23 #define SWRM_COMP_CFG_ADDR					0x04
25 #define SWRM_COMP_CFG_ENABLE_MSK				BIT(0)
26 #define SWRM_COMP_PARAMS					0x100
27 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK			GENMASK(4, 0)
29 #define SWRM_INTERRUPT_STATUS					0x200
30 #define SWRM_INTERRUPT_STATUS_RMSK				GENMASK(16, 0)
35 #define SWRM_INTERRUPT_MASK_ADDR				0x204
36 #define SWRM_INTERRUPT_CLEAR					0x208
37 #define SWRM_INTERRUPT_CPU_EN					0x210
38 #define SWRM_CMD_FIFO_WR_CMD					0x300
39 #define SWRM_CMD_FIFO_RD_CMD					0x304
40 #define SWRM_CMD_FIFO_CMD					0x308
41 #define SWRM_CMD_FIFO_STATUS					0x30C
42 #define SWRM_CMD_FIFO_CFG_ADDR					0x314
43 #define SWRM_RD_WR_CMD_RETRIES					0x7
44 #define SWRM_CMD_FIFO_RD_FIFO_ADDR				0x318
45 #define SWRM_ENUMERATOR_CFG_ADDR				0x500
46 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)		(0x101C + 0x40 * (m))
47 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK			GENMASK(2, 0)
49 #define SWRM_MCP_CFG_ADDR					0x1048
51 #define SWRM_DEF_CMD_NO_PINGS					0x1f
52 #define SWRM_MCP_STATUS						0x104C
53 #define SWRM_MCP_STATUS_BANK_NUM_MASK				BIT(0)
54 #define SWRM_MCP_SLV_STATUS					0x1090
55 #define SWRM_MCP_SLV_STATUS_MASK				GENMASK(1, 0)
56 #define SWRM_DP_PORT_CTRL_BANK(n, m)	(0x1124 + 0x100 * (n - 1) + 0x40 * m)
57 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)	(0x1138 + 0x100 * (n - 1) + 0x40 * m)
58 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT				0x18
59 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT				0x10
60 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT				0x08
61 #define SWRM_AHB_BRIDGE_WR_DATA_0				0xc85
62 #define SWRM_AHB_BRIDGE_WR_ADDR_0				0xc89
63 #define SWRM_AHB_BRIDGE_RD_ADDR_0				0xc8d
64 #define SWRM_AHB_BRIDGE_RD_DATA_0				0xc91
69 #define SWRM_SPECIAL_CMD_ID	0xF
72 #define QCOM_SWRM_MAX_RD_LEN	0xf
75 #define SWRM_MAX_DAIS		0xF
139 	if (ret < 0)  in qcom_swrm_ahb_reg_read()
144 	if (ret < 0)  in qcom_swrm_ahb_reg_read()
244 	for (i = 0; i < len; i++) {  in qcom_swrm_cmd_fifo_rd_cmd()
246 		rval[i] = val & 0xFF;  in qcom_swrm_cmd_fifo_rd_cmd()
264 	for (i = 0; i < SDW_MAX_DEVICES; i++) {  in qcom_swrm_get_device_status()
284 				    "CMD error, fifo status 0x%x\n",  in qcom_swrm_irq_handler()
286 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
317 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);  in qcom_swrm_init()
320 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);  in qcom_swrm_init()
344 	return 0;  in qcom_swrm_init()
354 		for (i = 0; i < msg->len;) {  in qcom_swrm_xfer_msg()
369 		for (i = 0; i < msg->len; i++) {  in qcom_swrm_xfer_msg()
400 	return 0;  in qcom_swrm_port_params()
440 		val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);  in qcom_swrm_port_enable()
463 	int i = 0;  in qcom_swrm_compute_params()
489 	return 0;  in qcom_swrm_compute_params()
539 	int i, maxport, pn, nports = 0, ret = 0;  in qcom_swrm_stream_alloc_ports()
582 		for (i = 0; i < nports; i++)  in qcom_swrm_stream_alloc_ports()
616 	return 0;  in qcom_swrm_hw_free()
626 	return 0;  in qcom_swrm_set_sdw_stream()
654 		if (ret < 0 && ret != -ENOTSUPP) {  in qcom_swrm_startup()
662 	return 0;  in qcom_swrm_startup()
700 	for (i = 0; i < num_dais; i++) {  in qcom_swrm_register_dais()
730 	u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };  in qcom_swrm_get_port_config()
775 	for (i = 0; i < nports; i++) {  in qcom_swrm_get_port_config()
782 	return 0;  in qcom_swrm_get_port_config()
815 		ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
820 	ctrl->irq = of_irq_get(dev->of_node, 0);
821 	if (ctrl->irq < 0) {
859 	prop->num_clk_gears = 0;
861 	prop->clk_freq = &qcom_swrm_freq_tbl[0];
890 		 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
891 		 ctrl->version & 0xffff);
893 	return 0;
910 	return 0;