346 	u32 sync_reg;  in intel_link_power_up()  local
373 		sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_link_power_up()
374 		u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);  in intel_link_power_up()
377 		sync_reg |= SDW_SHIM_SYNC_SYNCCPU;  in intel_link_power_up()
378 		intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_link_power_up()
581 	u32 sync_reg;  in intel_shim_sync_arm()  local
586 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_shim_sync_arm()
587 	sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);  in intel_shim_sync_arm()
588 	intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_shim_sync_arm()
596 	u32 sync_reg;  in intel_shim_sync_go_unlocked()  local
600 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_shim_sync_go_unlocked()
607 	sync_reg |= SDW_SHIM_SYNC_SYNCGO;  in intel_shim_sync_go_unlocked()
609 	ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,  in intel_shim_sync_go_unlocked()
848 	int sync_reg, ret;  in intel_post_bank_switch()  local
857 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_post_bank_switch()
867 	if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {  in intel_post_bank_switch()