Lines Matching +full:charge +full:- +full:ctrl +full:- +full:value
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
97 * struct xvcu_device - Xilinx VCU init device structure
115 * struct xvcu_pll_cfg - Helper data
117 * @cp: PLL charge pump control
237 * xvcu_read - Read from the VCU register space
241 * Return: Returns 32bit value from VCU register specified
250 * xvcu_write - Write to the VCU register space
253 * @value: Value to write
255 static inline void xvcu_write(void __iomem *iomem, u32 offset, u32 value) in xvcu_write() argument
257 iowrite32(value, iomem + offset); in xvcu_write()
261 * xvcu_write_field_reg - Write to the vcu reg field
280 * xvcu_set_vcu_pll_info - Set the VCU PLL info
287 * - When mcu or clock clock get from logicoreIP is 0
288 * - When VCU PLL DIV related bits value other than 1
289 * - When proper data not found for given data
290 * - When sis570_1 clocksource related operation failed
299 u32 cfg_val, mod, ctrl; in xvcu_set_vcu_pll_info() local
303 inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK); in xvcu_set_vcu_pll_info()
304 deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC); in xvcu_set_vcu_pll_info()
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
306 mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ; in xvcu_set_vcu_pll_info()
308 dev_err(xvcu->dev, "Invalid mcu and core clock data\n"); in xvcu_set_vcu_pll_info()
309 return -EINVAL; in xvcu_set_vcu_pll_info()
313 dev_dbg(xvcu->dev, "Ref clock from logicoreIP is %uHz\n", refclk); in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
315 dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk); in xvcu_set_vcu_pll_info()
317 clk_disable_unprepare(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
318 ret = clk_set_rate(xvcu->pll_ref, refclk); in xvcu_set_vcu_pll_info()
320 dev_warn(xvcu->dev, "failed to set logicoreIP refclk rate\n"); in xvcu_set_vcu_pll_info()
322 ret = clk_prepare_enable(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
324 dev_err(xvcu->dev, "failed to enable pll_ref clock source\n"); in xvcu_set_vcu_pll_info()
328 refclk = clk_get_rate(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
331 * The divide-by-2 should be always enabled (==1) in xvcu_set_vcu_pll_info()
335 vcu_pll_ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_CTRL); in xvcu_set_vcu_pll_info()
339 dev_err(xvcu->dev, "clkoutdiv value is invalid\n"); in xvcu_set_vcu_pll_info()
340 return -EINVAL; in xvcu_set_vcu_pll_info()
343 for (i = ARRAY_SIZE(xvcu_pll_cfg) - 1; i >= 0; i--) { in xvcu_set_vcu_pll_info()
346 fvco = cfg->fbdiv * refclk; in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
365 if (mcuclk - mod < LIMIT) in xvcu_set_vcu_pll_info()
373 dev_err(xvcu->dev, "Invalid clock combination.\n"); in xvcu_set_vcu_pll_info()
374 return -EINVAL; in xvcu_set_vcu_pll_info()
377 xvcu->coreclk = pll_clk / divisor_core; in xvcu_set_vcu_pll_info()
379 dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk); in xvcu_set_vcu_pll_info()
380 dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk); in xvcu_set_vcu_pll_info()
381 dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); in xvcu_set_vcu_pll_info()
384 vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) << in xvcu_set_vcu_pll_info()
394 xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, vcu_pll_ctrl); in xvcu_set_vcu_pll_info()
397 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL); in xvcu_set_vcu_pll_info()
398 ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT); in xvcu_set_vcu_pll_info()
399 ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) << in xvcu_set_vcu_pll_info()
401 ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT); in xvcu_set_vcu_pll_info()
402 ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; in xvcu_set_vcu_pll_info()
403 xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL, ctrl); in xvcu_set_vcu_pll_info()
405 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL); in xvcu_set_vcu_pll_info()
406 ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT); in xvcu_set_vcu_pll_info()
407 ctrl |= (divisor_core & VCU_PLL_DIVISOR_MASK) << in xvcu_set_vcu_pll_info()
409 ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT); in xvcu_set_vcu_pll_info()
410 ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; in xvcu_set_vcu_pll_info()
411 xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL, ctrl); in xvcu_set_vcu_pll_info()
413 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL); in xvcu_set_vcu_pll_info()
414 ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT); in xvcu_set_vcu_pll_info()
415 ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT; in xvcu_set_vcu_pll_info()
416 ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT); in xvcu_set_vcu_pll_info()
417 ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; in xvcu_set_vcu_pll_info()
418 xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL, ctrl); in xvcu_set_vcu_pll_info()
420 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL); in xvcu_set_vcu_pll_info()
421 ctrl &= ~(VCU_PLL_DIVISOR_MASK << VCU_PLL_DIVISOR_SHIFT); in xvcu_set_vcu_pll_info()
422 ctrl |= (divisor_mcu & VCU_PLL_DIVISOR_MASK) << VCU_PLL_DIVISOR_SHIFT; in xvcu_set_vcu_pll_info()
423 ctrl &= ~(VCU_SRCSEL_MASK << VCU_SRCSEL_SHIFT); in xvcu_set_vcu_pll_info()
424 ctrl |= (VCU_SRCSEL_PLL & VCU_SRCSEL_MASK) << VCU_SRCSEL_SHIFT; in xvcu_set_vcu_pll_info()
425 xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl); in xvcu_set_vcu_pll_info()
428 cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) | in xvcu_set_vcu_pll_info()
429 (found->cp << VCU_PLL_CFG_CP_SHIFT) | in xvcu_set_vcu_pll_info()
430 (found->lfhf << VCU_PLL_CFG_LFHF_SHIFT) | in xvcu_set_vcu_pll_info()
431 (found->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) | in xvcu_set_vcu_pll_info()
432 (found->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT); in xvcu_set_vcu_pll_info()
433 xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val); in xvcu_set_vcu_pll_info()
439 * xvcu_set_pll - PLL init sequence
455 dev_err(xvcu->dev, "failed to set pll info\n"); in xvcu_set_pll()
459 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
462 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
465 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
474 lock_status = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_STATUS); in xvcu_set_pll()
476 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
484 dev_err(xvcu->dev, "PLL is not locked\n"); in xvcu_set_pll()
485 return -ETIMEDOUT; in xvcu_set_pll()
489 * xvcu_probe - Probe existence of the logicoreIP
503 xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL); in xvcu_probe()
505 return -ENOMEM; in xvcu_probe()
507 xvcu->dev = &pdev->dev; in xvcu_probe()
510 dev_err(&pdev->dev, "get vcu_slcr memory resource failed.\n"); in xvcu_probe()
511 return -ENODEV; in xvcu_probe()
514 xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start, in xvcu_probe()
516 if (!xvcu->vcu_slcr_ba) { in xvcu_probe()
517 dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n"); in xvcu_probe()
518 return -ENOMEM; in xvcu_probe()
523 dev_err(&pdev->dev, "get logicore memory resource failed.\n"); in xvcu_probe()
524 return -ENODEV; in xvcu_probe()
527 xvcu->logicore_reg_ba = devm_ioremap(&pdev->dev, res->start, in xvcu_probe()
529 if (!xvcu->logicore_reg_ba) { in xvcu_probe()
530 dev_err(&pdev->dev, "logicore register mapping failed.\n"); in xvcu_probe()
531 return -ENOMEM; in xvcu_probe()
534 xvcu->aclk = devm_clk_get(&pdev->dev, "aclk"); in xvcu_probe()
535 if (IS_ERR(xvcu->aclk)) { in xvcu_probe()
536 dev_err(&pdev->dev, "Could not get aclk clock\n"); in xvcu_probe()
537 return PTR_ERR(xvcu->aclk); in xvcu_probe()
540 xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); in xvcu_probe()
541 if (IS_ERR(xvcu->pll_ref)) { in xvcu_probe()
542 dev_err(&pdev->dev, "Could not get pll_ref clock\n"); in xvcu_probe()
543 return PTR_ERR(xvcu->pll_ref); in xvcu_probe()
546 ret = clk_prepare_enable(xvcu->aclk); in xvcu_probe()
548 dev_err(&pdev->dev, "aclk clock enable failed\n"); in xvcu_probe()
552 ret = clk_prepare_enable(xvcu->pll_ref); in xvcu_probe()
554 dev_err(&pdev->dev, "pll_ref clock enable failed\n"); in xvcu_probe()
563 xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); in xvcu_probe()
568 dev_err(&pdev->dev, "Failed to set the pll\n"); in xvcu_probe()
572 dev_set_drvdata(&pdev->dev, xvcu); in xvcu_probe()
574 dev_info(&pdev->dev, "%s: Probed successfully\n", __func__); in xvcu_probe()
579 clk_disable_unprepare(xvcu->pll_ref); in xvcu_probe()
581 clk_disable_unprepare(xvcu->aclk); in xvcu_probe()
586 * xvcu_remove - Insert gasket isolation
599 return -ENODEV; in xvcu_remove()
602 xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); in xvcu_remove()
604 clk_disable_unprepare(xvcu->pll_ref); in xvcu_remove()
605 clk_disable_unprepare(xvcu->aclk); in xvcu_remove()
612 { .compatible = "xlnx,vcu-logicoreip-1.0" },
619 .name = "xilinx-vcu",