Lines Matching +full:0 +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
18 #define VCU_ECODER_ENABLE 0x00
19 #define VCU_DECODER_ENABLE 0x04
20 #define VCU_MEMORY_DEPTH 0x08
21 #define VCU_ENC_COLOR_DEPTH 0x0c
22 #define VCU_ENC_VERTICAL_RANGE 0x10
23 #define VCU_ENC_FRAME_SIZE_X 0x14
24 #define VCU_ENC_FRAME_SIZE_Y 0x18
25 #define VCU_ENC_COLOR_FORMAT 0x1c
26 #define VCU_ENC_FPS 0x20
27 #define VCU_MCU_CLK 0x24
28 #define VCU_CORE_CLK 0x28
29 #define VCU_PLL_BYPASS 0x2c
30 #define VCU_ENC_CLK 0x30
31 #define VCU_PLL_CLK 0x34
32 #define VCU_ENC_VIDEO_STANDARD 0x38
33 #define VCU_STATUS 0x3c
34 #define VCU_AXI_ENC_CLK 0x40
35 #define VCU_AXI_DEC_CLK 0x44
36 #define VCU_AXI_MCU_CLK 0x48
37 #define VCU_DEC_VIDEO_STANDARD 0x4c
38 #define VCU_DEC_FRAME_SIZE_X 0x50
39 #define VCU_DEC_FRAME_SIZE_Y 0x54
40 #define VCU_DEC_FPS 0x58
41 #define VCU_BUFFER_B_FRAME 0x5c
42 #define VCU_WPP_EN 0x60
43 #define VCU_PLL_CLK_DEC 0x64
44 #define VCU_GASKET_INIT 0x74
45 #define VCU_GASKET_VALUE 0x03
48 #define VCU_PLL_CTRL 0x24
49 #define VCU_PLL_CTRL_RESET_MASK 0x01
50 #define VCU_PLL_CTRL_RESET_SHIFT 0
51 #define VCU_PLL_CTRL_BYPASS_MASK 0x01
52 #define VCU_PLL_CTRL_BYPASS_SHIFT 3
53 #define VCU_PLL_CTRL_FBDIV_MASK 0x7f
55 #define VCU_PLL_CTRL_POR_IN_MASK 0x01
57 #define VCU_PLL_CTRL_PWR_POR_MASK 0x01
59 #define VCU_PLL_CTRL_CLKOUTDIV_MASK 0x03
61 #define VCU_PLL_CTRL_DEFAULT 0
64 #define VCU_PLL_CFG 0x28
65 #define VCU_PLL_CFG_RES_MASK 0x0f
66 #define VCU_PLL_CFG_RES_SHIFT 0
67 #define VCU_PLL_CFG_CP_MASK 0x0f
69 #define VCU_PLL_CFG_LFHF_MASK 0x03
71 #define VCU_PLL_CFG_LOCK_CNT_MASK 0x03ff
73 #define VCU_PLL_CFG_LOCK_DLY_MASK 0x7f
75 #define VCU_ENC_CORE_CTRL 0x30
76 #define VCU_ENC_MCU_CTRL 0x34
77 #define VCU_DEC_CORE_CTRL 0x38
78 #define VCU_DEC_MCU_CTRL 0x3c
79 #define VCU_PLL_DIVISOR_MASK 0x3f
81 #define VCU_SRCSEL_MASK 0x01
82 #define VCU_SRCSEL_SHIFT 0
85 #define VCU_PLL_STATUS 0x60
86 #define VCU_PLL_STATUS_LOCK_STATUS_MASK 0x01
91 #define DIVISOR_MIN 0
97 * struct xvcu_device - Xilinx VCU init device structure
115 * struct xvcu_pll_cfg - Helper data
133 { 25, 3, 10, 3, 63, 1000 },
134 { 26, 3, 10, 3, 63, 1000 },
135 { 27, 4, 6, 3, 63, 1000 },
136 { 28, 4, 6, 3, 63, 1000 },
137 { 29, 4, 6, 3, 63, 1000 },
138 { 30, 4, 6, 3, 63, 1000 },
139 { 31, 6, 1, 3, 63, 1000 },
140 { 32, 6, 1, 3, 63, 1000 },
141 { 33, 4, 10, 3, 63, 1000 },
142 { 34, 5, 6, 3, 63, 1000 },
143 { 35, 5, 6, 3, 63, 1000 },
144 { 36, 5, 6, 3, 63, 1000 },
145 { 37, 5, 6, 3, 63, 1000 },
146 { 38, 5, 6, 3, 63, 975 },
147 { 39, 3, 12, 3, 63, 950 },
148 { 40, 3, 12, 3, 63, 925 },
149 { 41, 3, 12, 3, 63, 900 },
150 { 42, 3, 12, 3, 63, 875 },
151 { 43, 3, 12, 3, 63, 850 },
152 { 44, 3, 12, 3, 63, 850 },
153 { 45, 3, 12, 3, 63, 825 },
154 { 46, 3, 12, 3, 63, 800 },
155 { 47, 3, 12, 3, 63, 775 },
156 { 48, 3, 12, 3, 63, 775 },
157 { 49, 3, 12, 3, 63, 750 },
158 { 50, 3, 12, 3, 63, 750 },
159 { 51, 3, 2, 3, 63, 725 },
160 { 52, 3, 2, 3, 63, 700 },
161 { 53, 3, 2, 3, 63, 700 },
162 { 54, 3, 2, 3, 63, 675 },
163 { 55, 3, 2, 3, 63, 675 },
164 { 56, 3, 2, 3, 63, 650 },
165 { 57, 3, 2, 3, 63, 650 },
166 { 58, 3, 2, 3, 63, 625 },
167 { 59, 3, 2, 3, 63, 625 },
168 { 60, 3, 2, 3, 63, 625 },
169 { 61, 3, 2, 3, 63, 600 },
170 { 62, 3, 2, 3, 63, 600 },
171 { 63, 3, 2, 3, 63, 600 },
172 { 64, 3, 2, 3, 63, 600 },
173 { 65, 3, 2, 3, 63, 600 },
174 { 66, 3, 2, 3, 63, 600 },
175 { 67, 3, 2, 3, 63, 600 },
176 { 68, 3, 2, 3, 63, 600 },
177 { 69, 3, 2, 3, 63, 600 },
178 { 70, 3, 2, 3, 63, 600 },
179 { 71, 3, 2, 3, 63, 600 },
180 { 72, 3, 2, 3, 63, 600 },
181 { 73, 3, 2, 3, 63, 600 },
182 { 74, 3, 2, 3, 63, 600 },
183 { 75, 3, 2, 3, 63, 600 },
184 { 76, 3, 2, 3, 63, 600 },
185 { 77, 3, 2, 3, 63, 600 },
186 { 78, 3, 2, 3, 63, 600 },
187 { 79, 3, 2, 3, 63, 600 },
188 { 80, 3, 2, 3, 63, 600 },
189 { 81, 3, 2, 3, 63, 600 },
190 { 82, 3, 2, 3, 63, 600 },
191 { 83, 4, 2, 3, 63, 600 },
192 { 84, 4, 2, 3, 63, 600 },
193 { 85, 4, 2, 3, 63, 600 },
194 { 86, 4, 2, 3, 63, 600 },
195 { 87, 4, 2, 3, 63, 600 },
196 { 88, 4, 2, 3, 63, 600 },
197 { 89, 4, 2, 3, 63, 600 },
198 { 90, 4, 2, 3, 63, 600 },
199 { 91, 4, 2, 3, 63, 600 },
200 { 92, 4, 2, 3, 63, 600 },
201 { 93, 4, 2, 3, 63, 600 },
202 { 94, 4, 2, 3, 63, 600 },
203 { 95, 4, 2, 3, 63, 600 },
204 { 96, 4, 2, 3, 63, 600 },
205 { 97, 4, 2, 3, 63, 600 },
206 { 98, 4, 2, 3, 63, 600 },
207 { 99, 4, 2, 3, 63, 600 },
208 { 100, 4, 2, 3, 63, 600 },
209 { 101, 4, 2, 3, 63, 600 },
210 { 102, 4, 2, 3, 63, 600 },
211 { 103, 5, 2, 3, 63, 600 },
212 { 104, 5, 2, 3, 63, 600 },
213 { 105, 5, 2, 3, 63, 600 },
214 { 106, 5, 2, 3, 63, 600 },
215 { 107, 3, 4, 3, 63, 600 },
216 { 108, 3, 4, 3, 63, 600 },
217 { 109, 3, 4, 3, 63, 600 },
218 { 110, 3, 4, 3, 63, 600 },
219 { 111, 3, 4, 3, 63, 600 },
220 { 112, 3, 4, 3, 63, 600 },
221 { 113, 3, 4, 3, 63, 600 },
222 { 114, 3, 4, 3, 63, 600 },
223 { 115, 3, 4, 3, 63, 600 },
224 { 116, 3, 4, 3, 63, 600 },
225 { 117, 3, 4, 3, 63, 600 },
226 { 118, 3, 4, 3, 63, 600 },
227 { 119, 3, 4, 3, 63, 600 },
228 { 120, 3, 4, 3, 63, 600 },
229 { 121, 3, 4, 3, 63, 600 },
230 { 122, 3, 4, 3, 63, 600 },
231 { 123, 3, 4, 3, 63, 600 },
232 { 124, 3, 4, 3, 63, 600 },
233 { 125, 3, 4, 3, 63, 600 },
237 * xvcu_read - Read from the VCU register space
250 * xvcu_write - Write to the VCU register space
261 * xvcu_write_field_reg - Write to the vcu reg field
280 * xvcu_set_vcu_pll_info - Set the VCU PLL info
287 * - When mcu or clock clock get from logicoreIP is 0
288 * - When VCU PLL DIV related bits value other than 1
289 * - When proper data not found for given data
290 * - When sis570_1 clocksource related operation failed
303 inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK); in xvcu_set_vcu_pll_info()
304 deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC); in xvcu_set_vcu_pll_info()
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
306 mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ; in xvcu_set_vcu_pll_info()
308 dev_err(xvcu->dev, "Invalid mcu and core clock data\n"); in xvcu_set_vcu_pll_info()
309 return -EINVAL; in xvcu_set_vcu_pll_info()
313 dev_dbg(xvcu->dev, "Ref clock from logicoreIP is %uHz\n", refclk); in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
315 dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk); in xvcu_set_vcu_pll_info()
317 clk_disable_unprepare(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
318 ret = clk_set_rate(xvcu->pll_ref, refclk); in xvcu_set_vcu_pll_info()
320 dev_warn(xvcu->dev, "failed to set logicoreIP refclk rate\n"); in xvcu_set_vcu_pll_info()
322 ret = clk_prepare_enable(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
324 dev_err(xvcu->dev, "failed to enable pll_ref clock source\n"); in xvcu_set_vcu_pll_info()
328 refclk = clk_get_rate(xvcu->pll_ref); in xvcu_set_vcu_pll_info()
331 * The divide-by-2 should be always enabled (==1) in xvcu_set_vcu_pll_info()
335 vcu_pll_ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_CTRL); in xvcu_set_vcu_pll_info()
339 dev_err(xvcu->dev, "clkoutdiv value is invalid\n"); in xvcu_set_vcu_pll_info()
340 return -EINVAL; in xvcu_set_vcu_pll_info()
343 for (i = ARRAY_SIZE(xvcu_pll_cfg) - 1; i >= 0; i--) { in xvcu_set_vcu_pll_info()
346 fvco = cfg->fbdiv * refclk; in xvcu_set_vcu_pll_info()
349 if (fvco % VCU_PLL_DIV2 != 0) in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
365 if (mcuclk - mod < LIMIT) in xvcu_set_vcu_pll_info()
373 dev_err(xvcu->dev, "Invalid clock combination.\n"); in xvcu_set_vcu_pll_info()
374 return -EINVAL; in xvcu_set_vcu_pll_info()
377 xvcu->coreclk = pll_clk / divisor_core; in xvcu_set_vcu_pll_info()
379 dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk); in xvcu_set_vcu_pll_info()
380 dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk); in xvcu_set_vcu_pll_info()
381 dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); in xvcu_set_vcu_pll_info()
384 vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) << in xvcu_set_vcu_pll_info()
394 xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, vcu_pll_ctrl); in xvcu_set_vcu_pll_info()
397 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL); in xvcu_set_vcu_pll_info()
403 xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_CORE_CTRL, ctrl); in xvcu_set_vcu_pll_info()
405 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL); in xvcu_set_vcu_pll_info()
411 xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_CORE_CTRL, ctrl); in xvcu_set_vcu_pll_info()
413 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL); in xvcu_set_vcu_pll_info()
418 xvcu_write(xvcu->vcu_slcr_ba, VCU_ENC_MCU_CTRL, ctrl); in xvcu_set_vcu_pll_info()
420 ctrl = xvcu_read(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL); in xvcu_set_vcu_pll_info()
425 xvcu_write(xvcu->vcu_slcr_ba, VCU_DEC_MCU_CTRL, ctrl); in xvcu_set_vcu_pll_info()
428 cfg_val = (found->res << VCU_PLL_CFG_RES_SHIFT) | in xvcu_set_vcu_pll_info()
429 (found->cp << VCU_PLL_CFG_CP_SHIFT) | in xvcu_set_vcu_pll_info()
430 (found->lfhf << VCU_PLL_CFG_LFHF_SHIFT) | in xvcu_set_vcu_pll_info()
431 (found->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) | in xvcu_set_vcu_pll_info()
432 (found->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT); in xvcu_set_vcu_pll_info()
433 xvcu_write(xvcu->vcu_slcr_ba, VCU_PLL_CFG, cfg_val); in xvcu_set_vcu_pll_info()
435 return 0; in xvcu_set_vcu_pll_info()
439 * xvcu_set_pll - PLL init sequence
455 dev_err(xvcu->dev, "failed to set pll info\n"); in xvcu_set_pll()
459 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
462 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
465 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
466 0, VCU_PLL_CTRL_RESET_MASK, in xvcu_set_pll()
474 lock_status = xvcu_read(xvcu->vcu_slcr_ba, VCU_PLL_STATUS); in xvcu_set_pll()
476 xvcu_write_field_reg(xvcu->vcu_slcr_ba, VCU_PLL_CTRL, in xvcu_set_pll()
477 0, VCU_PLL_CTRL_BYPASS_MASK, in xvcu_set_pll()
479 return 0; in xvcu_set_pll()
484 dev_err(xvcu->dev, "PLL is not locked\n"); in xvcu_set_pll()
485 return -ETIMEDOUT; in xvcu_set_pll()
489 * xvcu_probe - Probe existence of the logicoreIP
494 * Return: Returns 0 on success
503 xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL); in xvcu_probe()
505 return -ENOMEM; in xvcu_probe()
507 xvcu->dev = &pdev->dev; in xvcu_probe()
510 dev_err(&pdev->dev, "get vcu_slcr memory resource failed.\n"); in xvcu_probe()
511 return -ENODEV; in xvcu_probe()
514 xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start, in xvcu_probe()
516 if (!xvcu->vcu_slcr_ba) { in xvcu_probe()
517 dev_err(&pdev->dev, "vcu_slcr register mapping failed.\n"); in xvcu_probe()
518 return -ENOMEM; in xvcu_probe()
523 dev_err(&pdev->dev, "get logicore memory resource failed.\n"); in xvcu_probe()
524 return -ENODEV; in xvcu_probe()
527 xvcu->logicore_reg_ba = devm_ioremap(&pdev->dev, res->start, in xvcu_probe()
529 if (!xvcu->logicore_reg_ba) { in xvcu_probe()
530 dev_err(&pdev->dev, "logicore register mapping failed.\n"); in xvcu_probe()
531 return -ENOMEM; in xvcu_probe()
534 xvcu->aclk = devm_clk_get(&pdev->dev, "aclk"); in xvcu_probe()
535 if (IS_ERR(xvcu->aclk)) { in xvcu_probe()
536 dev_err(&pdev->dev, "Could not get aclk clock\n"); in xvcu_probe()
537 return PTR_ERR(xvcu->aclk); in xvcu_probe()
540 xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); in xvcu_probe()
541 if (IS_ERR(xvcu->pll_ref)) { in xvcu_probe()
542 dev_err(&pdev->dev, "Could not get pll_ref clock\n"); in xvcu_probe()
543 return PTR_ERR(xvcu->pll_ref); in xvcu_probe()
546 ret = clk_prepare_enable(xvcu->aclk); in xvcu_probe()
548 dev_err(&pdev->dev, "aclk clock enable failed\n"); in xvcu_probe()
552 ret = clk_prepare_enable(xvcu->pll_ref); in xvcu_probe()
554 dev_err(&pdev->dev, "pll_ref clock enable failed\n"); in xvcu_probe()
560 * Bit 0 : Gasket isolation in xvcu_probe()
563 xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); in xvcu_probe()
568 dev_err(&pdev->dev, "Failed to set the pll\n"); in xvcu_probe()
572 dev_set_drvdata(&pdev->dev, xvcu); in xvcu_probe()
574 dev_info(&pdev->dev, "%s: Probed successfully\n", __func__); in xvcu_probe()
576 return 0; in xvcu_probe()
579 clk_disable_unprepare(xvcu->pll_ref); in xvcu_probe()
581 clk_disable_unprepare(xvcu->aclk); in xvcu_probe()
586 * xvcu_remove - Insert gasket isolation
590 * Return: Returns 0 on success
599 return -ENODEV; in xvcu_remove()
602 xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); in xvcu_remove()
604 clk_disable_unprepare(xvcu->pll_ref); in xvcu_remove()
605 clk_disable_unprepare(xvcu->aclk); in xvcu_remove()
607 return 0; in xvcu_remove()
612 { .compatible = "xlnx,vcu-logicoreip-1.0" },
619 .name = "xilinx-vcu",