Lines Matching full:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
49 #include <soc/tegra/pmc.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
164 /* for secure PMC */
236 struct tegra_pmc *pmc; member
314 void (*init)(struct tegra_pmc *pmc);
315 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
340 * struct tegra_pmc - NVIDIA Tegra PMC
341 * @dev: pointer to PMC device structure
348 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
365 * @pctl_dev: pin controller exposed by the PMC
366 * @domain: IRQ domain provided by the PMC
408 static struct tegra_pmc *pmc = &(struct tegra_pmc) { variable
419 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_readl() argument
423 if (pmc->tz_only) { in tegra_pmc_readl()
427 if (pmc->dev) in tegra_pmc_readl()
428 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
438 return readl(pmc->base + offset); in tegra_pmc_readl()
441 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
446 if (pmc->tz_only) { in tegra_pmc_writel()
450 if (pmc->dev) in tegra_pmc_writel()
451 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
458 writel(value, pmc->base + offset); in tegra_pmc_writel()
462 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_scratch_readl() argument
464 if (pmc->tz_only) in tegra_pmc_scratch_readl()
465 return tegra_pmc_readl(pmc, offset); in tegra_pmc_scratch_readl()
467 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
470 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
473 if (pmc->tz_only) in tegra_pmc_scratch_writel()
474 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
476 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
486 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
487 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
489 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
492 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) in tegra_powergate_is_valid() argument
494 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
497 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) in tegra_powergate_is_available() argument
499 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
502 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) in tegra_powergate_lookup() argument
506 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
509 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
510 if (!tegra_powergate_is_valid(pmc, i)) in tegra_powergate_lookup()
513 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
522 * @pmc: power management controller
526 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra_powergate_set() argument
532 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
535 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
538 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
542 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra_powergate_set()
547 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
552 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, in __tegra_powergate_remove_clamping() argument
557 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
564 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
565 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
581 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); in __tegra_powergate_remove_clamping()
584 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
633 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
645 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
657 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
672 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
697 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
718 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
737 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
762 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_on()
765 return tegra_powergate_set(pmc, id, true); in tegra_powergate_power_on()
775 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_off()
778 return tegra_powergate_set(pmc, id, false); in tegra_powergate_power_off()
784 * @pmc: power management controller
787 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) in tegra_powergate_is_powered() argument
789 if (!tegra_powergate_is_valid(pmc, id)) in tegra_powergate_is_powered()
801 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_remove_clamping()
804 return __tegra_powergate_remove_clamping(pmc, id); in tegra_powergate_remove_clamping()
822 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_sequence_power_up()
833 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
837 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
848 * @pmc: power management controller
854 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, in tegra_get_cpu_powergate_id() argument
857 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
858 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
871 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_is_powered()
875 return tegra_powergate_is_powered(pmc, id); in tegra_pmc_cpu_is_powered()
886 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_power_on()
890 return tegra_powergate_set(pmc, id, true); in tegra_pmc_cpu_power_on()
901 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_remove_clamping()
914 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
928 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
931 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart_notify()
933 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart_notify()
951 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
952 status = tegra_powergate_is_powered(pmc, i); in powergate_show()
956 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
967 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
969 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
1014 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1049 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_powergate_add() argument
1051 struct device *dev = pmc->dev; in tegra_powergate_add()
1060 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1071 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1077 pg->pmc = pmc; in tegra_powergate_add()
1079 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1131 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1139 static int tegra_powergate_init(struct tegra_pmc *pmc, in tegra_powergate_init() argument
1150 err = tegra_powergate_add(pmc, child); in tegra_powergate_init()
1173 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1201 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_find() argument
1205 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1206 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1207 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1212 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, in tegra_io_pad_get_dpd_register_bit() argument
1220 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_dpd_register_bit()
1222 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1232 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1233 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1235 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1236 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1242 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_prepare() argument
1249 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); in tegra_io_pad_prepare()
1253 if (pmc->clk) { in tegra_io_pad_prepare()
1254 rate = pmc->rate; in tegra_io_pad_prepare()
1256 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1260 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); in tegra_io_pad_prepare()
1265 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1271 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, in tegra_io_pad_poll() argument
1279 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1289 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) in tegra_io_pad_unprepare() argument
1291 if (pmc->clk) in tegra_io_pad_unprepare()
1292 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); in tegra_io_pad_unprepare()
1307 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1309 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); in tegra_io_pad_power_enable()
1311 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1315 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); in tegra_io_pad_power_enable()
1317 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1319 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1323 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_enable()
1326 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1343 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1345 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); in tegra_io_pad_power_disable()
1347 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1351 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); in tegra_io_pad_power_disable()
1353 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); in tegra_io_pad_power_disable()
1355 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1359 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_disable()
1362 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1367 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_is_powered() argument
1373 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, in tegra_io_pad_is_powered()
1378 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1383 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_set_voltage() argument
1389 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_set_voltage()
1396 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1398 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1399 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1406 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1409 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1411 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1414 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1421 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1424 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1431 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_get_voltage() argument
1436 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_voltage()
1443 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1444 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1446 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1481 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1489 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1504 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1514 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1516 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); in tegra_pmc_enter_suspend_mode()
1518 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1520 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); in tegra_pmc_enter_suspend_mode()
1522 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1525 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1529 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_parse_dt() argument
1537 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1541 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1545 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1549 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1554 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1557 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1559 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1562 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1564 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1568 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1570 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1571 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1574 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1576 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1578 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1581 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1584 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1587 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1592 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1593 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1595 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1596 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1601 static void tegra_pmc_init(struct tegra_pmc *pmc) in tegra_pmc_init() argument
1603 if (pmc->soc->init) in tegra_pmc_init()
1604 pmc->soc->init(pmc); in tegra_pmc_init()
1607 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) in tegra_pmc_init_tsense_reset() argument
1611 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1615 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1618 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1647 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1649 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1653 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
1671 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
1673 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1675 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1677 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1685 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_groups_count() local
1687 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
1693 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); in tegra_io_pad_pinctrl_get_group_name() local
1695 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
1703 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_group_pins() local
1705 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
1723 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_get() local
1728 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_get()
1734 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
1742 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
1762 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_set() local
1769 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_set()
1790 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
1813 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) in tegra_pmc_pinctrl_init() argument
1817 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
1820 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
1821 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
1822 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
1824 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
1825 pmc); in tegra_pmc_pinctrl_init()
1826 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
1827 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
1828 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
1841 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
1842 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
1843 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
1845 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
1848 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
1858 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
1859 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
1860 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
1862 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
1865 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
1870 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) in tegra_pmc_reset_sysfs_init() argument
1872 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
1875 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
1883 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
1909 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc() local
1910 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
1929 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1933 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
1952 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1954 /* GPIO hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
1962 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
1976 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_wake() local
1984 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
1985 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
1987 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
1988 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
1990 /* enable PMC wake */ in tegra210_pmc_irq_set_wake()
1996 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2003 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2010 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_type() local
2022 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2043 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2050 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_wake() local
2058 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2061 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2068 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2071 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2078 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_type() local
2081 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2102 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2135 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) in tegra_pmc_irq_init() argument
2140 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2149 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2150 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2151 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2152 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2153 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2154 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2155 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2157 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2158 &tegra_pmc_irq_domain_ops, pmc); in tegra_pmc_irq_init()
2159 if (!pmc->domain) { in tegra_pmc_irq_init()
2160 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2170 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); in tegra_pmc_clk_notify_cb() local
2175 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2179 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2183 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2196 tegra_pmc_readl(pmc, offset); in pmc_clk_fence_udelay()
2197 /* pmc clk propagation delay 2 us */ in pmc_clk_fence_udelay()
2206 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2217 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2220 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2231 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2240 val = tegra_pmc_readl(pmc, offs); in pmc_clk_set_state()
2242 tegra_pmc_writel(pmc, val, offs); in pmc_clk_set_state()
2272 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, in tegra_pmc_clk_out_register() argument
2279 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2302 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2328 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, in tegra_pmc_clk_gate_register() argument
2335 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2352 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, in tegra_pmc_clock_register() argument
2360 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2361 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2367 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2371 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2381 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2384 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2386 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2388 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2395 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2404 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2405 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2406 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2412 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2418 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2423 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2431 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2442 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2457 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2460 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2472 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2473 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2474 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2476 pmc->wake = base; in tegra_pmc_probe()
2481 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2482 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2483 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2485 pmc->aotag = base; in tegra_pmc_probe()
2490 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2491 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2492 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2494 pmc->scratch = base; in tegra_pmc_probe()
2497 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
2498 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
2499 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
2506 pmc->clk = NULL; in tegra_pmc_probe()
2514 if (pmc->clk) { in tegra_pmc_probe()
2515 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2516 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2523 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2526 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2528 tegra_pmc_init(pmc); in tegra_pmc_probe()
2530 tegra_pmc_init_tsense_reset(pmc); in tegra_pmc_probe()
2532 tegra_pmc_reset_sysfs_init(pmc); in tegra_pmc_probe()
2547 err = tegra_pmc_pinctrl_init(pmc); in tegra_pmc_probe()
2551 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2555 err = tegra_pmc_irq_init(pmc); in tegra_pmc_probe()
2559 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2560 iounmap(pmc->base); in tegra_pmc_probe()
2561 pmc->base = base; in tegra_pmc_probe()
2562 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
2564 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2565 platform_set_drvdata(pdev, pmc); in tegra_pmc_probe()
2574 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
2578 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2586 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_suspend() local
2588 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); in tegra_pmc_suspend()
2595 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_resume() local
2597 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
2629 static void tegra20_pmc_init(struct tegra_pmc *pmc) in tegra20_pmc_init() argument
2634 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2636 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2638 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2640 if (pmc->sysclkreq_high) in tegra20_pmc_init()
2645 if (pmc->corereq_high) in tegra20_pmc_init()
2651 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2654 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2656 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2659 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
2660 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
2661 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
2662 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
2663 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
2665 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); in tegra20_pmc_init()
2669 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra20_pmc_setup_irq_polarity() argument
2675 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
2682 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3126 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra186_pmc_setup_irq_polarity() argument
3137 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3145 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3420 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3421 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3422 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3423 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3424 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3425 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3426 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3427 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3428 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3434 .name = "tegra-pmc",
3445 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) in tegra_pmc_detect_tz_only() argument
3449 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3456 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3457 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3461 pr_info("access to PMC is restricted to TZ\n"); in tegra_pmc_detect_tz_only()
3466 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3483 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
3490 * a PMC node. in tegra_pmc_early_init()
3493 * that didn't contain a PMC node. Note that in this case the in tegra_pmc_early_init()
3518 pr_err("failed to get PMC registers\n"); in tegra_pmc_early_init()
3524 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
3525 if (!pmc->base) { in tegra_pmc_early_init()
3526 pr_err("failed to map PMC registers\n"); in tegra_pmc_early_init()
3532 pmc->soc = match->data; in tegra_pmc_early_init()
3534 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
3535 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
3538 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3539 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
3540 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
3543 * Invert the interrupt polarity if a PMC device tree node in tegra_pmc_early_init()
3548 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()