Lines Matching +full:lp0 +full:- +full:vec
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
53 #include <dt-bindings/gpio/tegra186-gpio.h>
54 #include <dt-bindings/gpio/tegra194-gpio.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
328 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
340 * struct tegra_pmc - NVIDIA Tegra PMC
357 * @corereq_high: core power request is active-high
358 * @sysclkreq_high: system clock request is active-high
361 * @lp0_vec_phys: physical base address of the LP0 warm boot code
362 * @lp0_vec_size: size of the LP0 warm boot code
423 if (pmc->tz_only) { in tegra_pmc_readl()
427 if (pmc->dev) in tegra_pmc_readl()
428 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
438 return readl(pmc->base + offset); in tegra_pmc_readl()
446 if (pmc->tz_only) { in tegra_pmc_writel()
450 if (pmc->dev) in tegra_pmc_writel()
451 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
458 writel(value, pmc->base + offset); in tegra_pmc_writel()
464 if (pmc->tz_only) in tegra_pmc_scratch_readl()
467 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
473 if (pmc->tz_only) in tegra_pmc_scratch_writel()
476 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
486 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
494 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
499 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
506 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
507 return -EINVAL; in tegra_powergate_lookup()
509 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
513 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
517 return -ENODEV; in tegra_powergate_lookup()
521 * tegra_powergate_set() - set the state of a partition
532 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
533 return -EINVAL; in tegra_powergate_set()
535 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
538 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
547 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
557 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
564 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
584 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
593 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
594 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
602 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
603 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
611 while (i--) in tegra_powergate_enable_clocks()
612 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
627 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
633 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
645 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
651 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
657 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
658 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
672 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
687 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
697 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
706 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
718 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
724 pg->genpd.name, err); in tegra_genpd_power_on()
728 reset_control_release(pg->reset); in tegra_genpd_power_on()
737 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
740 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
749 pg->genpd.name, err); in tegra_genpd_power_off()
750 reset_control_release(pg->reset); in tegra_genpd_power_off()
757 * tegra_powergate_power_on() - power on partition
763 return -EINVAL; in tegra_powergate_power_on()
770 * tegra_powergate_power_off() - power off partition
776 return -EINVAL; in tegra_powergate_power_off()
783 * tegra_powergate_is_powered() - check if partition is powered
790 return -EINVAL; in tegra_powergate_is_powered()
796 * tegra_powergate_remove_clamping() - remove power clamps for partition
802 return -EINVAL; in tegra_powergate_remove_clamping()
809 * tegra_powergate_sequence_power_up() - power up partition
823 return -EINVAL; in tegra_powergate_sequence_power_up()
827 return -ENOMEM; in tegra_powergate_sequence_power_up()
829 pg->id = id; in tegra_powergate_sequence_power_up()
830 pg->clks = &clk; in tegra_powergate_sequence_power_up()
831 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
832 pg->reset = rst; in tegra_powergate_sequence_power_up()
833 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
837 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
847 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
857 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
858 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
860 return -EINVAL; in tegra_get_cpu_powergate_id()
864 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
879 * tegra_pmc_cpu_power_on() - power on CPU partition
894 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
914 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
924 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
928 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
949 seq_printf(s, "------------------\n"); in powergate_show()
951 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
956 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
967 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
969 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
970 return -ENOMEM; in tegra_powergate_debugfs_init()
984 return -ENODEV; in tegra_powergate_of_get_clks()
986 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
987 if (!pg->clks) in tegra_powergate_of_get_clks()
988 return -ENOMEM; in tegra_powergate_of_get_clks()
991 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
992 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
993 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
998 pg->num_clks = count; in tegra_powergate_of_get_clks()
1003 while (i--) in tegra_powergate_of_get_clks()
1004 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1006 kfree(pg->clks); in tegra_powergate_of_get_clks()
1014 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1017 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1018 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1019 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1024 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1031 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1033 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1037 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1042 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1043 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1051 struct device *dev = pmc->dev; in tegra_powergate_add()
1058 return -ENOMEM; in tegra_powergate_add()
1060 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1063 err = -ENODEV; in tegra_powergate_add()
1071 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1073 pg->id = id; in tegra_powergate_add()
1074 pg->genpd.name = np->name; in tegra_powergate_add()
1075 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1076 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1077 pg->pmc = pmc; in tegra_powergate_add()
1079 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1100 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1107 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1114 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1119 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1122 reset_control_put(pg->reset); in tegra_powergate_add()
1125 while (pg->num_clks--) in tegra_powergate_add()
1126 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1128 kfree(pg->clks); in tegra_powergate_add()
1131 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1166 reset_control_put(pg->reset); in tegra_powergate_remove()
1168 while (pg->num_clks--) in tegra_powergate_remove()
1169 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1171 kfree(pg->clks); in tegra_powergate_remove()
1173 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1205 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1206 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1207 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1222 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1223 return -ENOENT; in tegra_io_pad_get_dpd_register_bit()
1226 if (pad->dpd == UINT_MAX) in tegra_io_pad_get_dpd_register_bit()
1227 return -ENOTSUPP; in tegra_io_pad_get_dpd_register_bit()
1229 *mask = BIT(pad->dpd % 32); in tegra_io_pad_get_dpd_register_bit()
1231 if (pad->dpd < 32) { in tegra_io_pad_get_dpd_register_bit()
1232 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1233 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1235 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1236 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1253 if (pmc->clk) { in tegra_io_pad_prepare()
1254 rate = pmc->rate; in tegra_io_pad_prepare()
1256 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1257 return -ENODEV; in tegra_io_pad_prepare()
1286 return -ETIMEDOUT; in tegra_io_pad_poll()
1291 if (pmc->clk) in tegra_io_pad_unprepare()
1296 * tegra_io_pad_power_enable() - enable power to I/O pad
1307 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1311 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1319 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1326 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1332 * tegra_io_pad_power_disable() - disable power to I/O pad
1343 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1347 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1355 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1362 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1391 return -ENOENT; in tegra_io_pad_set_voltage()
1393 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1394 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1396 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1398 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1402 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1404 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1408 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1410 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1417 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1419 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1424 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1438 return -ENOENT; in tegra_io_pad_get_voltage()
1440 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1441 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1443 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1448 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1455 * tegra_io_rail_power_on() - enable power to I/O rail
1467 * tegra_io_rail_power_off() - disable power to I/O rail
1481 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1489 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1504 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1514 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1518 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1533 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1537 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1541 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1545 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1549 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1554 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1556 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1557 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1559 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1561 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1562 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1564 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1566 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1568 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1570 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1571 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1573 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1574 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1576 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1578 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1579 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1581 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1582 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1584 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1585 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1587 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1588 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1590 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1592 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1593 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1595 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1596 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1603 if (pmc->soc->init) in tegra_pmc_init()
1604 pmc->soc->init(pmc); in tegra_pmc_init()
1611 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1615 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1618 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1620 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1624 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1629 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1630 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1634 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1635 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1639 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1640 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1644 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1667 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1677 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1687 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
1695 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
1705 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
1730 return -EINVAL; in tegra_io_pad_pinconf_get()
1734 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
1742 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
1750 return -EINVAL; in tegra_io_pad_pinconf_get()
1771 return -EINVAL; in tegra_io_pad_pinconf_set()
1780 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
1782 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
1789 return -EINVAL; in tegra_io_pad_pinconf_set()
1790 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
1795 return -EINVAL; in tegra_io_pad_pinconf_set()
1817 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
1820 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
1821 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
1822 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
1824 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
1826 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
1827 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
1828 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
1841 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
1842 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
1843 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
1845 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
1848 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
1858 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
1859 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
1860 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
1862 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
1865 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
1872 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
1875 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
1883 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
1897 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
1898 return -EINVAL; in tegra_pmc_irq_translate()
1900 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
1901 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
1909 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
1910 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
1916 return -EINVAL; in tegra_pmc_irq_alloc()
1918 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
1919 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
1921 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
1924 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
1928 event->id, in tegra_pmc_irq_alloc()
1929 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1933 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
1936 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
1937 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
1945 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
1946 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
1947 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
1951 event->id, in tegra_pmc_irq_alloc()
1952 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1955 if (!err && domain->parent) in tegra_pmc_irq_alloc()
1956 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
1962 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
1963 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
1980 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
1981 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
1991 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2014 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2015 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2017 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2040 return -EINVAL; in tegra210_pmc_irq_set_type()
2054 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2055 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2058 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2061 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2068 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2071 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2081 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2099 return -EINVAL; in tegra186_pmc_irq_set_type()
2102 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2109 if (data->parent_data) in tegra_irq_mask_parent()
2115 if (data->parent_data) in tegra_irq_unmask_parent()
2121 if (data->parent_data) in tegra_irq_eoi_parent()
2129 if (data->parent_data) in tegra_irq_set_affinity_parent()
2132 return -EINVAL; in tegra_irq_set_affinity_parent()
2140 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2149 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2150 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2151 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2152 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2153 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2154 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2155 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2157 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2159 if (!pmc->domain) { in tegra_pmc_irq_init()
2160 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2161 return -ENOMEM; in tegra_pmc_irq_init()
2175 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2179 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2183 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2188 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2206 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2217 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2218 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2219 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2220 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2221 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2231 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2250 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2259 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2279 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2281 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2283 init.name = data->name; in tegra_pmc_clk_out_register()
2285 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2286 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2290 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2291 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2292 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2293 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2295 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2302 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2309 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2318 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2335 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2337 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2345 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2346 gate->offs = offset; in tegra_pmc_clk_gate_register()
2347 gate->shift = shift; in tegra_pmc_clk_gate_register()
2349 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2360 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2361 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2367 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2371 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2372 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2373 if (!clk_data->clks) in tegra_pmc_clock_register()
2376 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2379 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2381 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2384 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2388 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2389 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2393 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2395 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2397 data->name, err); in tegra_pmc_clock_register()
2401 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2404 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2412 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2423 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2431 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2437 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2442 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2457 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2458 return -ENODEV; in tegra_pmc_probe()
2460 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2466 base = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2472 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2473 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2474 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2476 pmc->wake = base; in tegra_pmc_probe()
2481 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2482 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2483 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2485 pmc->aotag = base; in tegra_pmc_probe()
2490 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2491 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2492 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2494 pmc->scratch = base; in tegra_pmc_probe()
2497 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
2498 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
2499 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
2501 if (err != -ENOENT) { in tegra_pmc_probe()
2502 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); in tegra_pmc_probe()
2506 pmc->clk = NULL; in tegra_pmc_probe()
2514 if (pmc->clk) { in tegra_pmc_probe()
2515 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2516 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2518 dev_err(&pdev->dev, in tegra_pmc_probe()
2523 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2526 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2542 dev_err(&pdev->dev, "unable to register restart handler, %d\n", in tegra_pmc_probe()
2551 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2559 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2560 iounmap(pmc->base); in tegra_pmc_probe()
2561 pmc->base = base; in tegra_pmc_probe()
2562 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
2564 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2570 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
2574 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
2576 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
2577 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
2578 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2640 if (pmc->sysclkreq_high) in tegra20_pmc_init()
2645 if (pmc->corereq_high) in tegra20_pmc_init()
2659 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
2660 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
2661 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
2662 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
2740 "LP0"
2887 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2889 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2890 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2891 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2892 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2974 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2983 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2996 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2997 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2998 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2999 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3000 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3004 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3010 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3025 "LP0",
3069 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3070 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3071 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3072 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3073 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3077 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3082 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3083 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3084 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3085 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3097 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3099 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3100 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3102 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3103 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3135 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3137 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3145 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3223 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3224 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3225 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3226 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3227 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3229 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3230 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3234 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3235 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3237 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3238 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3239 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3240 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3241 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3245 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3246 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3247 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3248 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3249 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3250 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3251 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3252 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3254 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3265 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3266 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3268 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3269 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3420 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3421 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3422 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3423 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3424 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3425 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3426 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3427 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3428 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3434 .name = "tegra-pmc",
3449 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3456 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3457 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3459 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
3466 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3483 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
3488 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
3489 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
3492 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
3508 * nice with multi-platform kernels. in tegra_pmc_early_init()
3520 return -ENXIO; in tegra_pmc_early_init()
3524 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
3525 if (!pmc->base) { in tegra_pmc_early_init()
3528 return -ENXIO; in tegra_pmc_early_init()
3532 pmc->soc = match->data; in tegra_pmc_early_init()
3534 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
3535 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
3538 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3539 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
3540 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
3544 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
3546 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
3548 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()