Lines Matching +full:geni +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
8 #include <linux/dma-mapping.h>
15 #include <linux/qcom-geni-se.h>
20 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
21 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
23 * like UART, SPI, I2C, I3C, etc.
29 * GENI based QUP is a highly-flexible and programmable module for supporting
30 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
35 * of a DMA Engine and GENI sub modules which enable serial engines to
39 * +-----------------------------------------+
41 * | +----------------------------+ |
42 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
44 * <---Clock Perf.----+ +----+-----------------------+ | |
48 * <--------AHB-------> | | | |
49 * | | +----+ |
52 * <------SE IRQ------+ +----------------------------+ |
54 * +-----------------------------------------+
56 * Figure 1: GENI based QUP Wrapper
58 * The GENI submodules include primary and secondary sequencers which are
60 * master-slave model, primary sequencer drives both TX & RX operations. On
61 * serial interfaces that operate using peer-to-peer model, primary sequencer
68 * GENI SE Wrapper driver is structured into 2 parts:
85 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
97 static const char * const icc_path_names[] = {"qup-core", "qup-config",
98 "qup-memory"};
180 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
187 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
189 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); in geni_se_get_qup_hw_version()
228 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
230 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
231 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
232 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
233 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
237 * geni_se_init() - Initialize the GENI serial engine
240 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
242 * This function is used to initialize the GENI serial engine, configure
243 * receive watermark and ready-for-receive watermarks.
250 geni_se_io_init(se->base); in geni_se_init()
251 geni_se_io_set_mode(se->base); in geni_se_init()
253 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
254 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
256 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
258 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
260 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
262 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
273 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
278 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
280 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
283 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
285 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
287 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
296 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
298 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
302 * geni_se_select_mode() - Select the serial engine transfer mode
327 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
331 * Refer to below examples for detailed bit-field description.
335 * +-----------+-------+-------+-------+-------+
337 * +-----------+-------+-------+-------+-------+
342 * +-----------+-------+-------+-------+-------+
346 * +-----------+-------+-------+-------+-------+
348 * +-----------+-------+-------+-------+-------+
353 * +-----------+-------+-------+-------+-------+
357 * +-----------+-------+-------+-------+-------+
359 * +-----------+-------+-------+-------+-------+
364 * +-----------+-------+-------+-------+-------+
375 * geni_se_config_packing() - Packing configuration of the serial engine
379 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
392 int idx_start = msb_to_lsb ? bpw - 1 : 0; in geni_se_config_packing()
394 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; in geni_se_config_packing()
403 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; in geni_se_config_packing()
413 temp_bpw = temp_bpw - BITS_PER_BYTE; in geni_se_config_packing()
416 cfg[iter - 1] |= PACKING_STOP_BIT; in geni_se_config_packing()
421 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
422 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
425 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
426 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
431 * 0 - 4x8, four words in each entry, max word size of 8 bits in geni_se_config_packing()
432 * 1 - 2x16, two words in each entry, max word size of 16 bits in geni_se_config_packing()
433 * 2 - 1x32, one word in each entry, max word size of 32 bits in geni_se_config_packing()
434 * 3 - undefined in geni_se_config_packing()
437 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
443 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_off()
445 clk_disable_unprepare(se->clk); in geni_se_clks_off()
446 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_off()
447 wrapper->ahb_clks); in geni_se_clks_off()
451 * geni_se_resources_off() - Turn off resources associated with the serial
461 if (has_acpi_companion(se->dev)) in geni_se_resources_off()
464 ret = pinctrl_pm_select_sleep_state(se->dev); in geni_se_resources_off()
476 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_on()
478 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
479 wrapper->ahb_clks); in geni_se_clks_on()
483 ret = clk_prepare_enable(se->clk); in geni_se_clks_on()
485 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
486 wrapper->ahb_clks); in geni_se_clks_on()
491 * geni_se_resources_on() - Turn on resources associated with the serial
501 if (has_acpi_companion(se->dev)) in geni_se_resources_on()
508 ret = pinctrl_pm_select_default_state(se->dev); in geni_se_resources_on()
517 * geni_se_clk_tbl_get() - Get the clock table to program DFS
534 if (se->clk_perf_tbl) { in geni_se_clk_tbl_get()
535 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
536 return se->num_clk_levels; in geni_se_clk_tbl_get()
539 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, in geni_se_clk_tbl_get()
540 sizeof(*se->clk_perf_tbl), in geni_se_clk_tbl_get()
542 if (!se->clk_perf_tbl) in geni_se_clk_tbl_get()
543 return -ENOMEM; in geni_se_clk_tbl_get()
546 freq = clk_round_rate(se->clk, freq + 1); in geni_se_clk_tbl_get()
547 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) in geni_se_clk_tbl_get()
549 se->clk_perf_tbl[i] = freq; in geni_se_clk_tbl_get()
551 se->num_clk_levels = i; in geni_se_clk_tbl_get()
552 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
553 return se->num_clk_levels; in geni_se_clk_tbl_get()
558 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
571 * - if @exact is true then @res_freq / <an_integer> == @req_freq
572 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
592 return -EINVAL; in geni_se_clk_freq_match()
597 new_delta = req_freq - tbl[i] / divider; in geni_se_clk_freq_match()
613 return -EINVAL; in geni_se_clk_freq_match()
624 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
637 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_prep()
641 return -EINVAL; in geni_se_tx_dma_prep()
643 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); in geni_se_tx_dma_prep()
644 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_tx_dma_prep()
645 return -EIO; in geni_se_tx_dma_prep()
650 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_dma_prep()
651 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_dma_prep()
652 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_dma_prep()
653 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_dma_prep()
654 writel_relaxed(len, se->base + SE_DMA_TX_LEN); in geni_se_tx_dma_prep()
660 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
673 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_prep()
677 return -EINVAL; in geni_se_rx_dma_prep()
679 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); in geni_se_rx_dma_prep()
680 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_rx_dma_prep()
681 return -EIO; in geni_se_rx_dma_prep()
686 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_dma_prep()
687 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_dma_prep()
688 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_dma_prep()
690 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_dma_prep()
691 writel_relaxed(len, se->base + SE_DMA_RX_LEN); in geni_se_rx_dma_prep()
697 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
706 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_unprep()
708 if (iova && !dma_mapping_error(wrapper->dev, iova)) in geni_se_tx_dma_unprep()
709 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); in geni_se_tx_dma_unprep()
714 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
723 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_unprep()
725 if (iova && !dma_mapping_error(wrapper->dev, iova)) in geni_se_rx_dma_unprep()
726 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); in geni_se_rx_dma_unprep()
733 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; in geni_icc_get()
735 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_get()
739 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); in geni_icc_get()
740 if (IS_ERR(se->icc_paths[i].path)) in geni_icc_get()
747 err = PTR_ERR(se->icc_paths[i].path); in geni_icc_get()
748 if (err != -EPROBE_DEFER) in geni_icc_get()
749 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", in geni_icc_get()
760 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_set_bw()
761 ret = icc_set_bw(se->icc_paths[i].path, in geni_icc_set_bw()
762 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); in geni_icc_set_bw()
764 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", in geni_icc_set_bw()
778 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) in geni_icc_set_tag()
779 icc_set_tag(se->icc_paths[i].path, tag); in geni_icc_set_tag()
788 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_enable()
789 ret = icc_enable(se->icc_paths[i].path); in geni_icc_enable()
791 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", in geni_icc_enable()
805 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_disable()
806 ret = icc_disable(se->icc_paths[i].path); in geni_icc_disable()
808 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", in geni_icc_disable()
829 parent = of_get_next_parent(wrapper->dev->of_node); in geni_remove_earlycon_icc_vote()
831 if (!of_device_is_compatible(child, "qcom,geni-se-qup")) in geni_remove_earlycon_icc_vote()
839 icc_put(wrapper->to_core.path); in geni_remove_earlycon_icc_vote()
840 wrapper->to_core.path = NULL; in geni_remove_earlycon_icc_vote()
851 struct device *dev = &pdev->dev; in geni_se_probe()
860 return -ENOMEM; in geni_se_probe()
862 wrapper->dev = dev; in geni_se_probe()
864 wrapper->base = devm_ioremap_resource(dev, res); in geni_se_probe()
865 if (IS_ERR(wrapper->base)) in geni_se_probe()
866 return PTR_ERR(wrapper->base); in geni_se_probe()
868 if (!has_acpi_companion(&pdev->dev)) { in geni_se_probe()
869 wrapper->ahb_clks[0].id = "m-ahb"; in geni_se_probe()
870 wrapper->ahb_clks[1].id = "s-ahb"; in geni_se_probe()
871 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); in geni_se_probe()
880 if (!strcmp(bcon->name, "qcom_geni")) { in geni_se_probe()
888 wrapper->to_core.path = devm_of_icc_get(dev, "qup-core"); in geni_se_probe()
889 if (IS_ERR(wrapper->to_core.path)) in geni_se_probe()
890 return PTR_ERR(wrapper->to_core.path); in geni_se_probe()
902 ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW, in geni_se_probe()
905 dev_err(&pdev->dev, "%s: ICC BW voting failed for core: %d\n", in geni_se_probe()
910 if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart")) in geni_se_probe()
912 of_node_put(pdev->dev.of_node); in geni_se_probe()
916 dev_dbg(dev, "GENI SE Driver probed\n"); in geni_se_probe()
921 { .compatible = "qcom,geni-se-qup", },
935 MODULE_DESCRIPTION("GENI Serial Engine Driver");