1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
12 #include <linux/reset-controller.h>
16 #include "ufshcd-pltfrm.h"
18 #include "ufs-qcom.h"
64 		dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",  in ufs_qcom_get_connected_tx_lanes()
84 	if (optional && err == -ENOENT) {  in ufs_qcom_host_clk_get()
89 	if (err != -EPROBE_DEFER)  in ufs_qcom_host_clk_get()
109 	if (!host->is_lane_clks_enabled)  in ufs_qcom_disable_lane_clks()
112 	clk_disable_unprepare(host->tx_l1_sync_clk);  in ufs_qcom_disable_lane_clks()
113 	clk_disable_unprepare(host->tx_l0_sync_clk);  in ufs_qcom_disable_lane_clks()
114 	clk_disable_unprepare(host->rx_l1_sync_clk);  in ufs_qcom_disable_lane_clks()
115 	clk_disable_unprepare(host->rx_l0_sync_clk);  in ufs_qcom_disable_lane_clks()
117 	host->is_lane_clks_enabled = false;  in ufs_qcom_disable_lane_clks()
123 	struct device *dev = host->hba->dev;  in ufs_qcom_enable_lane_clks()
125 	if (host->is_lane_clks_enabled)  in ufs_qcom_enable_lane_clks()
129 		host->rx_l0_sync_clk);  in ufs_qcom_enable_lane_clks()
134 		host->tx_l0_sync_clk);  in ufs_qcom_enable_lane_clks()
139 			host->rx_l1_sync_clk);  in ufs_qcom_enable_lane_clks()
144 			host->tx_l1_sync_clk);  in ufs_qcom_enable_lane_clks()
148 	host->is_lane_clks_enabled = true;  in ufs_qcom_enable_lane_clks()
152 	clk_disable_unprepare(host->rx_l1_sync_clk);  in ufs_qcom_enable_lane_clks()
154 	clk_disable_unprepare(host->tx_l0_sync_clk);  in ufs_qcom_enable_lane_clks()
156 	clk_disable_unprepare(host->rx_l0_sync_clk);  in ufs_qcom_enable_lane_clks()
164 	struct device *dev = host->hba->dev;  in ufs_qcom_init_lane_clks()
170 					&host->rx_l0_sync_clk, false);  in ufs_qcom_init_lane_clks()
175 					&host->tx_l0_sync_clk, false);  in ufs_qcom_init_lane_clks()
180 	if (host->hba->lanes_per_direction > 1) {  in ufs_qcom_init_lane_clks()
182 			&host->rx_l1_sync_clk, false);  in ufs_qcom_init_lane_clks()
187 			&host->tx_l1_sync_clk, true);  in ufs_qcom_init_lane_clks()
214 		/* sleep for max. 200us */  in ufs_qcom_check_hibern8()
229 		dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",  in ufs_qcom_check_hibern8()
233 		dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",  in ufs_qcom_check_hibern8()
242 	ufshcd_rmwl(host->hba, QUNIPRO_SEL,  in ufs_qcom_select_unipro_mode()
250  * ufs_qcom_host_reset - reset host controller and PHY
257 	if (!host->core_reset) {  in ufs_qcom_host_reset()
258 		dev_warn(hba->dev, "%s: reset control not set\n", __func__);  in ufs_qcom_host_reset()
262 	ret = reset_control_assert(host->core_reset);  in ufs_qcom_host_reset()
264 		dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",  in ufs_qcom_host_reset()
270 	 * The hardware requirement for delay between assert/deassert  in ufs_qcom_host_reset()
271 	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to  in ufs_qcom_host_reset()
272 	 * ~125us (4/32768). To be on the safe side add 200us delay.  in ufs_qcom_host_reset()
276 	ret = reset_control_deassert(host->core_reset);  in ufs_qcom_host_reset()
278 		dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",  in ufs_qcom_host_reset()
290 	struct phy *phy = host->generic_phy;  in ufs_qcom_power_up_sequence()
298 		dev_warn(hba->dev, "%s: host reset returned %d\n",  in ufs_qcom_power_up_sequence()
304 	/* phy initialization - calibrate the phy */  in ufs_qcom_power_up_sequence()
307 		dev_err(hba->dev, "%s: phy init failed, ret = %d\n",  in ufs_qcom_power_up_sequence()
312 	/* power on phy - start serdes and phy's power and clocks */  in ufs_qcom_power_up_sequence()
315 		dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",  in ufs_qcom_power_up_sequence()
332  * Internal hardware sub-modules within the UTP controller control the CGCs.
333  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
371 		dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);  in ufs_qcom_hce_enable_notify()
372 		err = -EINVAL;  in ufs_qcom_hce_enable_notify()
379  * Returns zero for success and non-zero in case of a failure
422 		dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);  in ufs_qcom_cfg_timers()
426 	list_for_each_entry(clki, &hba->clk_list_head, list) {  in ufs_qcom_cfg_timers()
427 		if (!strcmp(clki->name, "core_clk"))  in ufs_qcom_cfg_timers()
428 			core_clk_rate = clk_get_rate(clki->clk);  in ufs_qcom_cfg_timers()
457 				dev_err(hba->dev,  in ufs_qcom_cfg_timers()
463 			tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];  in ufs_qcom_cfg_timers()
466 				dev_err(hba->dev,  in ufs_qcom_cfg_timers()
472 			tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];  in ufs_qcom_cfg_timers()
474 			dev_err(hba->dev, "%s: invalid rate = %d\n",  in ufs_qcom_cfg_timers()
482 			dev_err(hba->dev,  in ufs_qcom_cfg_timers()
488 		tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];  in ufs_qcom_cfg_timers()
492 		dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);  in ufs_qcom_cfg_timers()
520 	ret = -EINVAL;  in ufs_qcom_cfg_timers()
535 			dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",  in ufs_qcom_link_startup_notify()
537 			err = -EINVAL;  in ufs_qcom_link_startup_notify()
574 	struct phy *phy = host->generic_phy;  in ufs_qcom_suspend()
595 	struct phy *phy = host->generic_phy;  in ufs_qcom_resume()
601 			dev_err(hba->dev, "%s: failed PHY power on: %d\n",  in ufs_qcom_resume()
620 	hba->is_sys_suspended = false;  in ufs_qcom_resume()
626 	if (host->dev_ref_clk_ctrl_mmio &&  in ufs_qcom_dev_ref_clk_ctrl()
627 	    (enable ^ host->is_dev_ref_clk_enabled)) {  in ufs_qcom_dev_ref_clk_ctrl()
628 		u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);  in ufs_qcom_dev_ref_clk_ctrl()
631 			temp |= host->dev_ref_clk_en_mask;  in ufs_qcom_dev_ref_clk_ctrl()
633 			temp &= ~host->dev_ref_clk_en_mask;  in ufs_qcom_dev_ref_clk_ctrl()
644 			gating_wait = host->hba->dev_info.clk_gating_wait_us;  in ufs_qcom_dev_ref_clk_ctrl()
652 				 * HS-MODE to LS-MODE or HIBERN8 state. Give it  in ufs_qcom_dev_ref_clk_ctrl()
653 				 * more delay to be on the safe side.  in ufs_qcom_dev_ref_clk_ctrl()
660 		writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);  in ufs_qcom_dev_ref_clk_ctrl()
667 		 * device ref_clk is stable for at least 1us before the hibern8  in ufs_qcom_dev_ref_clk_ctrl()
673 		host->is_dev_ref_clk_enabled = enable;  in ufs_qcom_dev_ref_clk_ctrl()
688 		ret = -EINVAL;  in ufs_qcom_pwr_change_notify()
708 		if (host->hw_ver.major == 0x1) {  in ufs_qcom_pwr_change_notify()
710 			 * HS-G3 operations may not reliably work on legacy QCOM  in ufs_qcom_pwr_change_notify()
714 			 * Hence downgrade the maximum supported gear to HS-G2.  in ufs_qcom_pwr_change_notify()
732 		if (!ufshcd_is_hs_mode(&hba->pwr_info) &&  in ufs_qcom_pwr_change_notify()
736 		if (host->hw_ver.major >= 0x4) {  in ufs_qcom_pwr_change_notify()
737 			if (dev_req_params->gear_tx == UFS_HS_G4) {  in ufs_qcom_pwr_change_notify()
751 		if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,  in ufs_qcom_pwr_change_notify()
752 					dev_req_params->pwr_rx,  in ufs_qcom_pwr_change_notify()
753 					dev_req_params->hs_rate, false)) {  in ufs_qcom_pwr_change_notify()
754 			dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",  in ufs_qcom_pwr_change_notify()
761 			ret = -EINVAL;  in ufs_qcom_pwr_change_notify()
765 		memcpy(&host->dev_req_params,  in ufs_qcom_pwr_change_notify()
769 		if (ufshcd_is_hs_mode(&hba->pwr_info) &&  in ufs_qcom_pwr_change_notify()
774 		ret = -EINVAL;  in ufs_qcom_pwr_change_notify()
803 	if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)  in ufs_qcom_apply_dev_quirks()
806 	if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)  in ufs_qcom_apply_dev_quirks()
807 		hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;  in ufs_qcom_apply_dev_quirks()
816 	if (host->hw_ver.major == 0x1)  in ufs_qcom_get_ufs_hci_version()
823  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
835 	if (host->hw_ver.major == 0x01) {  in ufs_qcom_advertise_quirks()
836 		hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS  in ufs_qcom_advertise_quirks()
840 		if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)  in ufs_qcom_advertise_quirks()
841 			hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;  in ufs_qcom_advertise_quirks()
843 		hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;  in ufs_qcom_advertise_quirks()
846 	if (host->hw_ver.major == 0x2) {  in ufs_qcom_advertise_quirks()
847 		hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;  in ufs_qcom_advertise_quirks()
851 			hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS  in ufs_qcom_advertise_quirks()
861 	hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;  in ufs_qcom_set_caps()
862 	hba->caps |= UFSHCD_CAP_CLK_SCALING;  in ufs_qcom_set_caps()
863 	hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;  in ufs_qcom_set_caps()
864 	hba->caps |= UFSHCD_CAP_WB_EN;  in ufs_qcom_set_caps()
865 	hba->caps |= UFSHCD_CAP_CRYPTO;  in ufs_qcom_set_caps()
867 	if (host->hw_ver.major >= 0x2) {  in ufs_qcom_set_caps()
868 		host->caps = UFS_QCOM_CAP_QUNIPRO |  in ufs_qcom_set_caps()
874  * ufs_qcom_setup_clocks - enables/disable clocks
879  * Returns 0 on success, non-zero on failure.
907 			if (ufshcd_is_hs_mode(&hba->pwr_info))  in ufs_qcom_setup_clocks()
923 	ufs_qcom_assert_reset(host->hba);  in ufs_qcom_reset_assert()
924 	/* provide 1ms delay to let the reset pulse propagate. */  in ufs_qcom_reset_assert()
936 	ufs_qcom_deassert_reset(host->hba);  in ufs_qcom_reset_deassert()
964  * ufs_qcom_init - bind phy with controller
970  * Returns -EPROBE_DEFER if binding fails, returns negative error
976 	struct device *dev = hba->dev;  in ufs_qcom_init()
982 		return -ENODEV;  in ufs_qcom_init()
986 		err = -ENOMEM;  in ufs_qcom_init()
992 	host->hba = hba;  in ufs_qcom_init()
996 	host->core_reset = devm_reset_control_get(hba->dev, "rst");  in ufs_qcom_init()
997 	if (IS_ERR(host->core_reset)) {  in ufs_qcom_init()
998 		err = PTR_ERR(host->core_reset);  in ufs_qcom_init()
1000 		host->core_reset = NULL;  in ufs_qcom_init()
1004 	/* Fire up the reset controller. Failure here is non-fatal. */  in ufs_qcom_init()
1005 	host->rcdev.of_node = dev->of_node;  in ufs_qcom_init()
1006 	host->rcdev.ops = &ufs_qcom_reset_ops;  in ufs_qcom_init()
1007 	host->rcdev.owner = dev->driver->owner;  in ufs_qcom_init()
1008 	host->rcdev.nr_resets = 1;  in ufs_qcom_init()
1009 	err = devm_reset_controller_register(dev, &host->rcdev);  in ufs_qcom_init()
1020 	host->generic_phy = devm_phy_get(dev, "ufsphy");  in ufs_qcom_init()
1022 	if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {  in ufs_qcom_init()
1027 		err = -EPROBE_DEFER;  in ufs_qcom_init()
1031 	} else if (IS_ERR(host->generic_phy)) {  in ufs_qcom_init()
1033 			host->generic_phy = NULL;  in ufs_qcom_init()
1035 			err = PTR_ERR(host->generic_phy);  in ufs_qcom_init()
1041 	host->device_reset = devm_gpiod_get_optional(dev, "reset",  in ufs_qcom_init()
1043 	if (IS_ERR(host->device_reset)) {  in ufs_qcom_init()
1044 		err = PTR_ERR(host->device_reset);  in ufs_qcom_init()
1045 		if (err != -EPROBE_DEFER)  in ufs_qcom_init()
1050 	ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,  in ufs_qcom_init()
1051 		&host->hw_ver.minor, &host->hw_ver.step);  in ufs_qcom_init()
1057 	if (host->hw_ver.major >= 0x02) {  in ufs_qcom_init()
1058 		host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;  in ufs_qcom_init()
1059 		host->dev_ref_clk_en_mask = BIT(26);  in ufs_qcom_init()
1065 			host->dev_ref_clk_ctrl_mmio =  in ufs_qcom_init()
1067 			if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {  in ufs_qcom_init()
1069 					"%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",  in ufs_qcom_init()
1071 					PTR_ERR(host->dev_ref_clk_ctrl_mmio));  in ufs_qcom_init()
1072 				host->dev_ref_clk_ctrl_mmio = NULL;  in ufs_qcom_init()
1074 			host->dev_ref_clk_en_mask = BIT(5);  in ufs_qcom_init()
1091 	if (hba->dev->id < MAX_UFS_QCOM_HOSTS)  in ufs_qcom_init()
1092 		ufs_qcom_hosts[hba->dev->id] = host;  in ufs_qcom_init()
1094 	host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;  in ufs_qcom_init()
1116 	phy_power_off(host->generic_phy);  in ufs_qcom_exit()
1117 	phy_exit(host->generic_phy);  in ufs_qcom_exit()
1127 		return -EINVAL;  in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1205 	struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;  in ufs_qcom_clk_scale_notify()
1223 				    dev_req_params->gear_rx,  in ufs_qcom_clk_scale_notify()
1224 				    dev_req_params->pwr_rx,  in ufs_qcom_clk_scale_notify()
1225 				    dev_req_params->hs_rate,  in ufs_qcom_clk_scale_notify()
1245 		dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);  in ufs_qcom_print_hw_debug_reg_all()
1250 	if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))  in ufs_qcom_print_hw_debug_reg_all()
1269 	/* clear bit 17 - UTP_DBG_RAMS_EN */  in ufs_qcom_print_hw_debug_reg_all()
1296 	if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {  in ufs_qcom_enable_test_bus()
1297 		ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,  in ufs_qcom_enable_test_bus()
1299 		ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);  in ufs_qcom_enable_test_bus()
1301 		ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);  in ufs_qcom_enable_test_bus()
1302 		ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);  in ufs_qcom_enable_test_bus()
1309 	host->testbus.select_major = TSTBUS_UNIPRO;  in ufs_qcom_get_default_testbus_cfg()
1310 	host->testbus.select_minor = 37;  in ufs_qcom_get_default_testbus_cfg()
1315 	if (host->testbus.select_major >= TSTBUS_MAX) {  in ufs_qcom_testbus_cfg_is_ok()
1316 		dev_err(host->hba->dev,  in ufs_qcom_testbus_cfg_is_ok()
1318 			__func__, host->testbus.select_major);  in ufs_qcom_testbus_cfg_is_ok()
1332 		return -EINVAL;  in ufs_qcom_testbus_config()
1335 		return -EPERM;  in ufs_qcom_testbus_config()
1337 	switch (host->testbus.select_major) {  in ufs_qcom_testbus_config()
1394 	ufshcd_rmwl(host->hba, TEST_BUS_SEL,  in ufs_qcom_testbus_config()
1395 		    (u32)host->testbus.select_major << 19,  in ufs_qcom_testbus_config()
1397 	ufshcd_rmwl(host->hba, mask,  in ufs_qcom_testbus_config()
1398 		    (u32)host->testbus.select_minor << offset,  in ufs_qcom_testbus_config()
1419  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1420  * @hba: per-adapter instance
1429 	if (!host->device_reset)  in ufs_qcom_device_reset()
1433 	 * The UFS device shall detect reset pulses of 1us, sleep for 10us to  in ufs_qcom_device_reset()
1436 	gpiod_set_value_cansleep(host->device_reset, 1);  in ufs_qcom_device_reset()
1439 	gpiod_set_value_cansleep(host->device_reset, 0);  in ufs_qcom_device_reset()
1454 	p->polling_ms = 60;  in ufs_qcom_config_scaling_param()
1455 	d->upthreshold = 70;  in ufs_qcom_config_scaling_param()
1456 	d->downdifferential = 5;  in ufs_qcom_config_scaling_param()
1467  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1492  * ufs_qcom_probe - probe routine of the driver
1495  * Return zero for success and non-zero for failure
1500 	struct device *dev = &pdev->dev;  in ufs_qcom_probe()
1511  * ufs_qcom_remove - set driver_data of the device to NULL
1520 	pm_runtime_get_sync(&(pdev)->dev);  in ufs_qcom_remove()
1552 		.name	= "ufshcd-qcom",