1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
12 #include "ufshcd-crypto.h"
13 #include "ufs-qcom.h"
29 /* QCOM ICE v3.X only */
34 /* QCOM ICE v2.X only */
54 /* BIST ("built-in self-test"?) status flags */
61 #define qcom_ice_writel(host, val, reg)	\  argument
62 	writel((val), (host)->ice_mmio + (reg))
63 #define qcom_ice_readl(host, reg)	\  argument
64 	readl((host)->ice_mmio + (reg))
66 static bool qcom_ice_supported(struct ufs_qcom_host *host)  in qcom_ice_supported()  argument
68 	struct device *dev = host->hba->dev;  in qcom_ice_supported()
69 	u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION);  in qcom_ice_supported()
74 	/* For now this driver only supports ICE version 3. */  in qcom_ice_supported()
85 	regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING);  in qcom_ice_supported()
95 int ufs_qcom_ice_init(struct ufs_qcom_host *host)  in ufs_qcom_ice_init()  argument
97 	struct ufs_hba *hba = host->hba;  in ufs_qcom_ice_init()
98 	struct device *dev = hba->dev;  in ufs_qcom_ice_init()
118 	host->ice_mmio = devm_ioremap_resource(dev, res);  in ufs_qcom_ice_init()
119 	if (IS_ERR(host->ice_mmio)) {  in ufs_qcom_ice_init()
120 		err = PTR_ERR(host->ice_mmio);  in ufs_qcom_ice_init()
125 	if (!qcom_ice_supported(host))  in ufs_qcom_ice_init()
132 	hba->caps &= ~UFSHCD_CAP_CRYPTO;  in ufs_qcom_ice_init()
136 static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host)  in qcom_ice_low_power_mode_enable()  argument
140 	regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);  in qcom_ice_low_power_mode_enable()
143 	 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0  in qcom_ice_low_power_mode_enable()
146 	qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);  in qcom_ice_low_power_mode_enable()
149 static void qcom_ice_optimization_enable(struct ufs_qcom_host *host)  in qcom_ice_optimization_enable()  argument
154 	regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);  in qcom_ice_optimization_enable()
158 	qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);  in qcom_ice_optimization_enable()
162 int ufs_qcom_ice_enable(struct ufs_qcom_host *host)  in ufs_qcom_ice_enable()  argument
164 	if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))  in ufs_qcom_ice_enable()
166 	qcom_ice_low_power_mode_enable(host);  in ufs_qcom_ice_enable()
167 	qcom_ice_optimization_enable(host);  in ufs_qcom_ice_enable()
168 	return ufs_qcom_ice_resume(host);  in ufs_qcom_ice_enable()
172 static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host)  in qcom_ice_wait_bist_status()  argument
178 		reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS);  in qcom_ice_wait_bist_status()
184 		return -ETIMEDOUT;  in qcom_ice_wait_bist_status()
188 int ufs_qcom_ice_resume(struct ufs_qcom_host *host)  in ufs_qcom_ice_resume()  argument
192 	if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))  in ufs_qcom_ice_resume()
195 	err = qcom_ice_wait_bist_status(host);  in ufs_qcom_ice_resume()
197 		dev_err(host->hba->dev, "BIST status error (%d)\n", err);  in ufs_qcom_ice_resume()
205  * vendor-specific SCM calls for this; it doesn't support the standard way.
218 	if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE))  in ufs_qcom_ice_program_key()
221 	/* Only AES-256-XTS has been tested so far. */  in ufs_qcom_ice_program_key()
222 	cap = hba->crypto_cap_array[cfg->crypto_cap_idx];  in ufs_qcom_ice_program_key()
225 		dev_err_ratelimited(hba->dev,  in ufs_qcom_ice_program_key()
228 		return -EINVAL;  in ufs_qcom_ice_program_key()
231 	memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);  in ufs_qcom_ice_program_key()
234 	 * The SCM call byte-swaps the 32-bit words of the key.  So we have to  in ufs_qcom_ice_program_key()
242 				   cfg->data_unit_size);  in ufs_qcom_ice_program_key()