25 	int err = 0;  in ufs_hisi_check_hibern8()
26 	u32 tx_fsm_val_0 = 0;  in ufs_hisi_check_hibern8()
27 	u32 tx_fsm_val_1 = 0;  in ufs_hisi_check_hibern8()
31 		err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),  in ufs_hisi_check_hibern8()
48 		err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),  in ufs_hisi_check_hibern8()
94 	ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,  in ufs_hisi_soc_init()
132 	ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);  in ufs_hisi_soc_init()
146 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
148 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);  in ufs_hisi_link_startup_pre_change()
150 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
152 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);  in ufs_hisi_link_startup_pre_change()
154 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
158 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);  in ufs_hisi_link_startup_pre_change()
160 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
164 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
166 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);  in ufs_hisi_link_startup_pre_change()
168 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);  in ufs_hisi_link_startup_pre_change()
170 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);  in ufs_hisi_link_startup_pre_change()
172 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);  in ufs_hisi_link_startup_pre_change()
174 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);  in ufs_hisi_link_startup_pre_change()
176 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);  in ufs_hisi_link_startup_pre_change()
178 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
180 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
181 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
185 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);  in ufs_hisi_link_startup_pre_change()
187 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);  in ufs_hisi_link_startup_pre_change()
189 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);  in ufs_hisi_link_startup_pre_change()
191 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);  in ufs_hisi_link_startup_pre_change()
194 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);  in ufs_hisi_link_startup_pre_change()
196 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);  in ufs_hisi_link_startup_pre_change()
200 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);  in ufs_hisi_link_startup_pre_change()
202 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);  in ufs_hisi_link_startup_pre_change()
204 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);  in ufs_hisi_link_startup_pre_change()
206 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);  in ufs_hisi_link_startup_pre_change()
208 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);  in ufs_hisi_link_startup_pre_change()
210 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);  in ufs_hisi_link_startup_pre_change()
212 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);  in ufs_hisi_link_startup_pre_change()
214 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);  in ufs_hisi_link_startup_pre_change()
216 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);  in ufs_hisi_link_startup_pre_change()
218 	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);  in ufs_hisi_link_startup_pre_change()
219 	if (value != 0x1)  in ufs_hisi_link_startup_pre_change()
221 		    "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);  in ufs_hisi_link_startup_pre_change()
224 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);  in ufs_hisi_link_startup_pre_change()
240 	ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);  in ufs_hisi_link_startup_pre_change()
241 	ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);  in ufs_hisi_link_startup_pre_change()
242 	if (value != 0) {  in ufs_hisi_link_startup_pre_change()
255 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);  in ufs_hisi_link_startup_post_change()
257 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);  in ufs_hisi_link_startup_post_change()
259 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);  in ufs_hisi_link_startup_post_change()
268 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);  in ufs_hisi_link_startup_post_change()
270 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);  in ufs_hisi_link_startup_post_change()
272 	return 0;  in ufs_hisi_link_startup_post_change()
278 	int err = 0;  in ufs_hisi_link_startup_notify()
316 		 * Boston platform need to set SaveConfigTime to 0x13,  in ufs_hisi_pwr_change_pre_change()
320 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);  in ufs_hisi_pwr_change_pre_change()
322 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);  in ufs_hisi_pwr_change_pre_change()
324 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);  in ufs_hisi_pwr_change_pre_change()
326 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);  in ufs_hisi_pwr_change_pre_change()
328 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);  in ufs_hisi_pwr_change_pre_change()
330 		ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);  in ufs_hisi_pwr_change_pre_change()
331 		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);  in ufs_hisi_pwr_change_pre_change()
335 		pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");  in ufs_hisi_pwr_change_pre_change()
337 		ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);  in ufs_hisi_pwr_change_pre_change()
339 		ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);  in ufs_hisi_pwr_change_pre_change()
343 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);  in ufs_hisi_pwr_change_pre_change()
345 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);  in ufs_hisi_pwr_change_pre_change()
346 	/*PA_PWRModeUserData0 = 8191, default is 0*/  in ufs_hisi_pwr_change_pre_change()
347 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);  in ufs_hisi_pwr_change_pre_change()
348 	/*PA_PWRModeUserData1 = 65535, default is 0*/  in ufs_hisi_pwr_change_pre_change()
349 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);  in ufs_hisi_pwr_change_pre_change()
350 	/*PA_PWRModeUserData2 = 32767, default is 0*/  in ufs_hisi_pwr_change_pre_change()
351 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);  in ufs_hisi_pwr_change_pre_change()
352 	/*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/  in ufs_hisi_pwr_change_pre_change()
353 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);  in ufs_hisi_pwr_change_pre_change()
354 	/*DME_TC0ReplayTimeOutVal = 65535, default is 0*/  in ufs_hisi_pwr_change_pre_change()
355 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);  in ufs_hisi_pwr_change_pre_change()
356 	/*DME_AFC0ReqTimeOutVal = 32767, default is 0*/  in ufs_hisi_pwr_change_pre_change()
357 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);  in ufs_hisi_pwr_change_pre_change()
358 	/*PA_PWRModeUserData3 = 8191, default is 0*/  in ufs_hisi_pwr_change_pre_change()
359 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);  in ufs_hisi_pwr_change_pre_change()
360 	/*PA_PWRModeUserData4 = 65535, default is 0*/  in ufs_hisi_pwr_change_pre_change()
361 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);  in ufs_hisi_pwr_change_pre_change()
362 	/*PA_PWRModeUserData5 = 32767, default is 0*/  in ufs_hisi_pwr_change_pre_change()
363 	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);  in ufs_hisi_pwr_change_pre_change()
364 	/*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/  in ufs_hisi_pwr_change_pre_change()
365 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);  in ufs_hisi_pwr_change_pre_change()
366 	/*DME_TC1ReplayTimeOutVal = 65535, default is 0*/  in ufs_hisi_pwr_change_pre_change()
367 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);  in ufs_hisi_pwr_change_pre_change()
368 	/*DME_AFC1ReqTimeOutVal = 32767, default is 0*/  in ufs_hisi_pwr_change_pre_change()
369 	ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);  in ufs_hisi_pwr_change_pre_change()
378 	int ret = 0;  in ufs_hisi_pwr_change_notify()
415 		return 0;  in ufs_hisi_suspend()
419 		return 0;  in ufs_hisi_suspend()
424 	/* set ref_dig_clk override of PHY PCS to 0 */  in ufs_hisi_suspend()
425 	ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);  in ufs_hisi_suspend()
429 	return 0;  in ufs_hisi_suspend()
437 		return 0;  in ufs_hisi_resume()
440 	ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);  in ufs_hisi_resume()
445 	return 0;  in ufs_hisi_resume()
470 	int err = 0;  in ufs_hisi_init_common()
495 	return 0;  in ufs_hisi_init_common()
500 	int ret = 0;  in ufs_hi3660_init()
513 	return 0;  in ufs_hi3660_init()
518 	int ret = 0;  in ufs_hi3670_init()
536 	return 0;  in ufs_hi3670_init()
579 	return 0;  in ufs_hisi_remove()