Lines Matching refs:UIC_ARG_MIB_SEL
159 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
161 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
168 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); in exynos7_ufs_pre_link()
188 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
419 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
421 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
423 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
425 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
427 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
429 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
431 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
433 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
438 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
440 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
442 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
444 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
446 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
448 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
450 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
452 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
455 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
472 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
475 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
478 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
481 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
484 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
487 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
494 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); in exynos_ufs_config_phy_cap_attr()
498 UIC_ARG_MIB_SEL(RX_MIN_ACTIVATETIME_CAP, in exynos_ufs_config_phy_cap_attr()
503 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), in exynos_ufs_config_phy_cap_attr()
510 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, in exynos_ufs_config_phy_cap_attr()
516 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
522 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, in exynos_ufs_config_phy_cap_attr()
600 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); in exynos_ufs_config_sync_pattern_mask()