Lines Matching +full:0 +full:x05000000
45 #define FE_LED0 (1<<0)
88 #define ISCON 0x10 /* connected to scsi */
89 #define CRST 0x08 /* force reset */
90 #define IARB 0x02 /* immediate arbitration */
93 #define SDU 0x80 /* cmd: disconnect will raise error */
94 #define CHM 0x40 /* sta: chained mode */
95 #define WSS 0x08 /* sta: wide scsi send [W]*/
96 #define WSR 0x01 /* sta: wide scsi received [W]*/
99 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
100 #define ULTRA 0x80 /* cmd: ULTRA enable */
101 /* bits 0-2, 7 rsvd for C1010 */
104 #define RRE 0x40 /* r/w:e enable response to resel. */
105 #define SRE 0x20 /* r/w:e enable response to select */
117 #define CREQ 0x80 /* r/w: SCSI-REQ */
118 #define CACK 0x40 /* r/w: SCSI-ACK */
119 #define CBSY 0x20 /* r/w: SCSI-BSY */
120 #define CSEL 0x10 /* r/w: SCSI-SEL */
121 #define CATN 0x08 /* r/w: SCSI-ATN */
122 #define CMSG 0x04 /* r/w: SCSI-MSG */
123 #define CC_D 0x02 /* r/w: SCSI-C_D */
124 #define CI_O 0x01 /* r/w: SCSI-I_O */
126 /*0a*/ u8 nc_ssid;
128 /*0b*/ u8 nc_sbcl;
130 /*0c*/ u8 nc_dstat;
131 #define DFE 0x80 /* sta: dma fifo empty */
132 #define MDPE 0x40 /* int: master data parity error */
133 #define BF 0x20 /* int: script: bus fault */
134 #define ABRT 0x10 /* int: script: command aborted */
135 #define SSI 0x08 /* int: script: single step */
136 #define SIR 0x04 /* int: script: interrupt instruct. */
137 #define IID 0x01 /* int: script: illegal instruct. */
139 /*0d*/ u8 nc_sstat0;
140 #define ILF 0x80 /* sta: data in SIDL register lsb */
141 #define ORF 0x40 /* sta: data in SODR register lsb */
142 #define OLF 0x20 /* sta: data in SODL register lsb */
143 #define AIP 0x10 /* sta: arbitration in progress */
144 #define LOA 0x08 /* sta: arbitration lost */
145 #define WOA 0x04 /* sta: arbitration won */
146 #define IRST 0x02 /* sta: scsi reset signal */
147 #define SDP 0x01 /* sta: scsi parity signal */
149 /*0e*/ u8 nc_sstat1;
150 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
152 /*0f*/ u8 nc_sstat2;
153 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
154 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
155 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
156 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
157 #define LDSC 0x02 /* sta: disconnect & reconnect */
165 #define CABRT 0x80 /* cmd: abort current operation */
166 #define SRST 0x40 /* mod: reset chip */
167 #define SIGP 0x20 /* r/w: message from host to script */
168 #define SEM 0x10 /* r/w: message between host + script */
169 #define CON 0x08 /* sta: connected to scsi */
170 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
171 #define SIP 0x02 /* sta: scsi-interrupt */
172 #define DIP 0x01 /* sta: host/script interrupt */
175 #define FLSH 0x04 /* sta: chip is flushing */
176 #define SCRUN 0x02 /* sta: scripts are running */
177 #define SIRQD 0x01 /* r/w: disable INT pin */
186 #define CSIGP 0x40
187 /* bits 0-2,7 rsvd for C1010 */
190 #define FLF 0x08 /* cmd: flush dma fifo */
191 #define CLF 0x04 /* cmd: clear dma fifo */
192 #define FM 0x02 /* mod: fetch pin mode */
193 #define WRIE 0x01 /* mod: write and invalidate enable */
200 #define BDIS 0x80 /* mod: burst disable */
201 #define MPEE 0x08 /* mod: master parity error enable */
204 #define DFS 0x20 /* mod: dma fifo size */
205 /* bits 0-1, 3-7 rsvd for C1010 */
220 #define BL_2 0x80 /* mod: burst length shift value +2 */
221 #define BL_1 0x40 /* mod: burst length shift value +1 */
222 #define ERL 0x08 /* mod: enable read line */
223 #define ERMP 0x04 /* mod: enable read multiple */
224 #define BOF 0x02 /* mod: burst op code fetch */
230 #define CLSE 0x80 /* mod: cache line size enable */
231 #define PFF 0x40 /* cmd: pre-fetch flush */
232 #define PFEN 0x20 /* mod: pre-fetch enable */
233 #define SSM 0x10 /* mod: single step mode */
234 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
235 #define STD 0x04 /* cmd: start dma mode */
236 #define IRQD 0x02 /* mod: irq disable */
237 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
238 /* bits 0-1 rsvd for C1010 */
244 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
245 #define STO 0x0400/* sta: timeout (select) */
246 #define GEN 0x0200/* sta: timeout (general) */
247 #define HTH 0x0100/* sta: timeout (handshake) */
248 #define MA 0x80 /* sta: phase mismatch */
249 #define CMP 0x40 /* sta: arbitration complete */
250 #define SEL 0x20 /* sta: selected by another device */
251 #define RSL 0x10 /* sta: reselected by another device*/
252 #define SGE 0x08 /* sta: gross error (over/underflow)*/
253 #define UDC 0x04 /* sta: unexpected disconnect */
254 #define RST 0x02 /* sta: scsi bus reset detected */
255 #define PAR 0x01 /* sta: scsi parity error */
268 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
269 #define DBLEN 0x08 /* clock doubler running */
270 #define DBLSEL 0x04 /* clock doubler selected */
274 #define ROF 0x40 /* reset scsi offset (after gross error!) */
275 #define EXT 0x02 /* extended filtering */
278 #define TE 0x80 /* c: tolerAnt enable */
279 #define HSC 0x20 /* c: Halt SCSI Clock */
280 #define CSF 0x02 /* c: clear scsi fifo */
284 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
285 #define SMODE_HVD 0x40 /* High Voltage Differential */
286 #define SMODE_SE 0x80 /* Single Ended */
287 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
288 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
289 /* bits 0-5 rsvd for C1010 */
293 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
294 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
295 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
296 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
297 #define DISFC 0x10 /* Disable Auto FIFO Clear */
298 #define DILS 0x02 /* Disable Internal Load/Store */
299 #define DPR 0x01 /* Disable Pipe Req */
302 #define ZMOD 0x80 /* High Impedance Mode */
303 #define DDAC 0x08 /* Disable Dual Address Cycle */
304 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
305 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
306 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
325 #define U3EN 0x80 /* Enable Ultra 3 */
326 #define AIPCKEN 0x40 /* AIP checking enable */
328 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
329 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
330 #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
331 #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
332 /*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
334 #define DISAIP 0x08 /* Disable AIP generation C10-66 only */
356 #define SNDCRC 0x10 /* Send CRC Request */
381 #define SCR_DATA_OUT 0x00000000
382 #define SCR_DATA_IN 0x01000000
383 #define SCR_COMMAND 0x02000000
384 #define SCR_STATUS 0x03000000
385 #define SCR_DT_DATA_OUT 0x04000000
386 #define SCR_DT_DATA_IN 0x05000000
387 #define SCR_MSG_OUT 0x06000000
388 #define SCR_MSG_IN 0x07000000
390 #define SCR_ILG_OUT 0x04000000
391 #define SCR_ILG_IN 0x05000000
411 #define OPC_MOVE 0x08000000
413 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
414 /* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */
415 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
417 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
418 /* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */
419 #define SCR_CHMOV_TBL (0x10000000)
424 #define OPC_TCHMOVE 0x08000000
426 #define SCR_TCHMOVE_ABS(l) ((0x20000000 | OPC_TCHMOVE) | (l))
427 #define SCR_TCHMOVE_TBL (0x30000000 | OPC_TCHMOVE)
429 #define SCR_TMOV_ABS(l) ((0x20000000) | (l))
430 #define SCR_TMOV_TBL (0x30000000)
444 * SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
453 #define SCR_SEL_ABS 0x40000000
454 #define SCR_SEL_ABS_ATN 0x41000000
455 #define SCR_SEL_TBL 0x42000000
456 #define SCR_SEL_TBL_ATN 0x43000000
459 #define SCR_RESEL_ABS 0x40000000
460 #define SCR_RESEL_ABS_ATN 0x41000000
461 #define SCR_RESEL_TBL 0x42000000
462 #define SCR_RESEL_TBL_ATN 0x43000000
472 #define SCR_JMP_REL 0x04000000
490 #define SCR_WAIT_DISC 0x48000000
491 #define SCR_WAIT_RESEL 0x50000000
494 #define SCR_DISCONNECT 0x48000000
510 #define SCR_SET(f) (0x58000000 | (f))
511 #define SCR_CLR(f) (0x60000000 | (f))
513 #define SCR_CARRY 0x00000400
514 #define SCR_TRG 0x00000200
515 #define SCR_ACK 0x00000040
516 #define SCR_ATN 0x00000008
538 #define SCR_NO_FLUSH 0x01000000
540 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
541 #define SCR_COPY_F(n) (0xc0000000 | (n))
550 * << 0 >>
553 * << 0 >>
556 * << 0 >>
563 * offset 0x80. Bit 7 of register offset is stored in
569 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
572 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
575 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
578 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
581 #define SCR_LOAD 0x00000000
582 #define SCR_SHL 0x01000000
583 #define SCR_OR 0x02000000
584 #define SCR_XOR 0x03000000
585 #define SCR_AND 0x04000000
586 #define SCR_SHR 0x05000000
587 #define SCR_ADD 0x06000000
588 #define SCR_ADDC 0x07000000
590 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
595 * << 0 >>
598 * << 0 >>
601 * << 0 >>
604 * << 0 >>
610 SCR_REG_SFBR(reg,SCR_OR,0)
613 SCR_SFBR_REG(reg,SCR_OR,0)
639 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
640 #define SCR_NO_FLUSH2 0x02000000
641 #define SCR_DSA_REL2 0x10000000
644 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
647 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
651 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
656 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
696 #define SCR_NO_OP 0x80000000
697 #define SCR_JUMP 0x80080000
698 #define SCR_JUMP64 0x80480000
699 #define SCR_JUMPR 0x80880000
700 #define SCR_CALL 0x88080000
701 #define SCR_CALLR 0x88880000
702 #define SCR_RETURN 0x90080000
703 #define SCR_INT 0x98080000
704 #define SCR_INT_FLY 0x98180000
706 #define IFFALSE(arg) (0x00080000 | (arg))
707 #define IFTRUE(arg) (0x00000000 | (arg))
709 #define WHEN(phase) (0x00030000 | (phase))
710 #define IF(phase) (0x00020000 | (phase))
712 #define DATA(D) (0x00040000 | ((D) & 0xff))
713 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
715 #define CARRYSET (0x00200000)
745 #define M_TERMINATE (0x11)
759 #define PPR_OPT_IU (0x01)
760 #define PPR_OPT_DT (0x02)
761 #define PPR_OPT_QAS (0x04)
762 #define PPR_OPT_MASK (0x07)
777 #define S_ILLEGAL (0xff)