Lines Matching refs:DMA_CSR
23 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ macro
66 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)) in sun3x_esp_irq_pending()
75 val = dma_read32(DMA_CSR); in sun3x_esp_reset_dma()
76 dma_write32(val | DMA_RST_SCSI, DMA_CSR); in sun3x_esp_reset_dma()
77 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR); in sun3x_esp_reset_dma()
80 val = dma_read32(DMA_CSR); in sun3x_esp_reset_dma()
81 dma_write32(val | DMA_INT_ENAB, DMA_CSR); in sun3x_esp_reset_dma()
89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
93 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sun3x_esp_dma_drain()
96 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) { in sun3x_esp_dma_drain()
112 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) { in sun3x_esp_dma_invalidate()
123 dma_write32(val, DMA_CSR); in sun3x_esp_dma_invalidate()
125 dma_write32(val, DMA_CSR); in sun3x_esp_dma_invalidate()
137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
151 u32 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_error()
253 val = dma_read32(DMA_CSR); in esp_sun3x_remove()
254 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR); in esp_sun3x_remove()