Lines Matching full:risc
401 #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */
409 #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */
463 /* RISC processor status register */
466 #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */
479 /* RISC processor memory timing register */
487 #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */
488 #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */
489 #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */
490 #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */
493 #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */
497 #define HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */
498 #define HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */