1371 	uint64_t off8, val, mem_crb, word[2] = {0, 0};  in qla4_82xx_pci_mem_read_2M()  local
1378 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_read_2M()
1380 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_read_2M()
1398 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_read_2M()
1400 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_read_2M()
1402 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1404 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1407 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_read_2M()
1423 				mem_crb + MIU_TEST_AGT_RDDATA(k));  in qla4_82xx_pci_mem_read_2M()
1462 	uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};  in qla4_82xx_pci_mem_write_2M()  local
1468 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_write_2M()
1470 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_write_2M()
1523 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1525 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1527 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1529 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1531 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,  in qla4_82xx_pci_mem_write_2M()
1534 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,  in qla4_82xx_pci_mem_write_2M()
1538 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1540 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1543 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_write_2M()