1201 	wrt_reg_dword(&reg->ctrl_status,  in qla24xx_unprotect_flash()
1202 	    rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_unprotect_flash()
1203 	rd_reg_dword(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_unprotect_flash()
1244 	wrt_reg_dword(&reg->ctrl_status,  in qla24xx_protect_flash()
1245 	    rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_protect_flash()
1470 	wrt_reg_dword(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1471 	    rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1472 	rd_reg_dword(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1494 	wrt_reg_dword(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1495 	    rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1496 	rd_reg_dword(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1974 	data = rd_reg_word(&reg->ctrl_status);  in qla2x00_flash_enable()
1976 	wrt_reg_word(&reg->ctrl_status, data);  in qla2x00_flash_enable()
1977 	rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_enable()
1990 	data = rd_reg_word(&reg->ctrl_status);  in qla2x00_flash_disable()
1992 	wrt_reg_word(&reg->ctrl_status, data);  in qla2x00_flash_disable()
1993 	rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_disable()
2012 	bank_select = rd_reg_word(&reg->ctrl_status);  in qla2x00_read_flash_byte()
2020 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2021 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2032 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2033 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2037 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
2038 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2072 	bank_select = rd_reg_word(&reg->ctrl_status);  in qla2x00_write_flash_byte()
2079 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2080 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2083 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2085 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2093 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2094 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2098 		wrt_reg_word(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2099 		rd_reg_word(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2108 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2110 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2403 	wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);  in qla2x00_write_optrom_data()