2231 		if (rd_reg_word(&reg->mailbox12) & BIT_0)  in qla2x00_initialize_adapter()
2369 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2100_pci_config()
2413 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2421 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2431 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2436 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
2451 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2602 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
2608 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
2614 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2618 		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */  in qla2x00_reset_chip()
2623 			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */  in qla2x00_reset_chip()
2628 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2647 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2651 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2655 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2673 			if ((rd_reg_word(&reg->ctrl_status) &  in qla2x00_reset_chip()
2688 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
2707 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2776 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
2777 	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
2792 	    rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
2838 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
2839 	for (cnt = 60; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
2853 	     rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3010 		data = rd_reg_word(&reg->ctrl_status);  in qla2x00_chip_diag()
3691 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
3801 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4049 	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */  in qla2x00_config_rings()
4133 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
4606 		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)  in qla2x00_nvram_config()
7137 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7139 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()