Lines Matching +full:0 +full:xdc000
14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
78 /* Bits 15-0 of word 0 */
80 /* Bits 15-0 of word 3 */
86 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
87 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
110 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
111 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
162 * BIT 0 = Control Enable
165 * BIT 0-7 = Reserved
170 * BIT 0-7 = Reserved
175 * BIT 0-7 = Reserved
200 * BIT 0 = Enable spinup delay
242 * BIT 0 = Selective Login
362 * BIT 0 = Enable Hard Loop Id
383 * BIT 0 = Operation Mode bit 0
387 * BIT 4 = Connection Options bit 0
404 * BIT 0 = Reserved
408 * BIT 4 = FCP RSP Payload bit 0
418 * BIT 13 = Data Rate bit 0
423 * BIT 29 = Enable response queue 0 in index shadowing
424 * BIT 30 = Enable request queue 0 out index shadowing
436 #define COMMAND_BIDIRECTIONAL 0x75
473 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
511 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
522 #define FW_MAX_TIMEOUT 0x1999
540 #define TSK_SIMPLE 0
557 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
590 uint16_t reserved_1; /* MUST be set to 0. */
597 #define STATUS_TYPE 0x03 /* Status entry. */
656 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
657 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
658 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
659 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
660 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
665 #define MARKER_TYPE 0x04 /* Marker entry. */
676 uint8_t modifier; /* Modifier (7-0). */
677 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
694 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
725 #define PURX_ELS_HEADER_SIZE 0x18
730 #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
772 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
802 #define EPD_ELS_COMMAND (0 << 13)
814 __le64 tx_address __packed; /* DSD 0 address. */
815 __le32 tx_len; /* DSD 0 length. */
866 #define MBX_IOCB_TYPE 0x39
879 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
889 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
907 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
908 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
909 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
910 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
911 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
912 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
913 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
923 #define LSC_SCODE_NOLINK 0x01
924 #define LSC_SCODE_NOIOCB 0x02
925 #define LSC_SCODE_NOXCB 0x03
926 #define LSC_SCODE_CMD_FAILED 0x04
927 #define LSC_SCODE_NOFABRIC 0x05
928 #define LSC_SCODE_FW_NOT_READY 0x07
929 #define LSC_SCODE_NOT_LOGGED_IN 0x09
930 #define LSC_SCODE_NOPCB 0x0A
932 #define LSC_SCODE_ELS_REJECT 0x18
933 #define LSC_SCODE_CMD_PARAM_ERR 0x19
934 #define LSC_SCODE_PORTID_USED 0x1A
935 #define LSC_SCODE_NPORT_USED 0x1B
936 #define LSC_SCODE_NONPORT 0x1C
937 #define LSC_SCODE_LOGGED_IN 0x1D
938 #define LSC_SCODE_NOFLOGI_ACC 0x1F
941 #define TSK_MGMT_IOCB_TYPE 0x14
976 #define ABORT_IOCB_TYPE 0x33
1002 #define ABTS_RCV_TYPE 0x54
1003 #define ABTS_RSP_TYPE 0x55
1010 __le32 handle; /* type 0x55 only */
1012 __le16 comp_status; /* type 0x55 only */
1013 __le16 nport_handle; /* type 0x54 only */
1015 __le16 control_flags; /* type 0x55 only */
1066 #define BA_RJT_EXP_NO_ADDITIONAL 0
1076 #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
1079 #define FC_TYPE_BLD 0x000 /* Basic link data */
1080 #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
1081 #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
1082 #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
1083 #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
1084 #define FC_ROUTING_BLD 0x80 /* Basic link data frame */
1085 #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
1093 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1094 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1095 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
1096 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
1098 #define FA_NVRAM_FUNC0_ADDR 0x80
1099 #define FA_NVRAM_FUNC1_ADDR 0x180
1101 #define FA_NVRAM_VPD_SIZE 0x200
1102 #define FA_NVRAM_VPD0_ADDR 0x00
1103 #define FA_NVRAM_VPD1_ADDR 0x100
1105 #define FA_BOOT_CODE_ADDR 0x00000
1111 #define FA_RISC_CODE_ADDR 0x20000
1114 #define FA_FLASH_DESCR_ADDR_24 0x11000
1115 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
1116 #define FA_NPIV_CONF0_ADDR_24 0x16000
1117 #define FA_NPIV_CONF1_ADDR_24 0x17000
1119 #define FA_FW_AREA_ADDR 0x40000
1120 #define FA_VPD_NVRAM_ADDR 0x48000
1121 #define FA_FEATURE_ADDR 0x4C000
1122 #define FA_FLASH_DESCR_ADDR 0x50000
1123 #define FA_FLASH_LAYOUT_ADDR 0x50400
1124 #define FA_HW_EVENT0_ADDR 0x54000
1125 #define FA_HW_EVENT1_ADDR 0x54400
1126 #define FA_HW_EVENT_SIZE 0x200
1128 #define FA_NPIV_CONF0_ADDR 0x5C000
1129 #define FA_NPIV_CONF1_ADDR 0x5D000
1130 #define FA_FCP_PRIO0_ADDR 0x10000
1131 #define FA_FCP_PRIO1_ADDR 0x12000
1136 #define HW_EVENT_RESET_ERR 0xF00B
1137 #define HW_EVENT_ISP_ERR 0xF020
1138 #define HW_EVENT_PARITY_ERR 0xF022
1139 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1140 #define HW_EVENT_FLASH_FW_ERR 0xF024
1151 #define PBM_PCI_33MHZ (0 << 8)
1161 #define MWB_512_BYTES (0 << 4)
1204 #define HCCRX_NOOP 0x00000000
1206 #define HCCRX_SET_RISC_RESET 0x10000000
1208 #define HCCRX_CLR_RISC_RESET 0x20000000
1210 #define HCCRX_SET_RISC_PAUSE 0x30000000
1212 #define HCCRX_REL_RISC_PAUSE 0x40000000
1214 #define HCCRX_SET_HOST_INT 0x50000000
1216 #define HCCRX_CLR_HOST_INT 0x60000000
1218 #define HCCRX_CLR_RISC_INT 0xA0000000
1295 #define RISC_REGISTER_BASE_OFFSET 0x7010
1296 #define RISC_REGISTER_WINDOW_OFFSET 0x6
1298 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1300 #define RISC_SEMAPHORE 0x1UL
1302 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1305 #define RISC_SEMAPHORE_FORCE 0x8000UL
1307 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1318 #define TC_AEN_DISABLE 0
1324 #define TC_FCE_OPTIONS 0
1339 * BIT 0 = Enable Hard Loop Id
1384 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1396 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1397 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1398 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1401 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1402 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1403 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1404 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1405 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1420 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1435 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1436 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1437 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1438 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1439 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1442 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1443 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1467 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1493 uint8_t vp_idx; /* Format 0=reserved */
1494 uint8_t vp_status; /* Format 0=reserved */
1500 /* format 0 loop */
1508 #define TOPO_MASK 0xE
1509 #define TOPO_FL 0x2
1510 #define TOPO_N2N 0x4
1511 #define TOPO_F 0x6
1546 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1565 __le64 tx_address __packed; /* Data segment 0 address. */
1566 uint32_t tx_len; /* Data segment 0 length. */
1616 #define FLT_REG_FW 0x01
1617 #define FLT_REG_BOOT_CODE 0x07
1618 #define FLT_REG_VPD_0 0x14
1619 #define FLT_REG_NVRAM_0 0x15
1620 #define FLT_REG_VPD_1 0x16
1621 #define FLT_REG_NVRAM_1 0x17
1622 #define FLT_REG_VPD_2 0xD4
1623 #define FLT_REG_NVRAM_2 0xD5
1624 #define FLT_REG_VPD_3 0xD6
1625 #define FLT_REG_NVRAM_3 0xD7
1626 #define FLT_REG_FDT 0x1a
1627 #define FLT_REG_FLT 0x1c
1628 #define FLT_REG_HW_EVENT_0 0x1d
1629 #define FLT_REG_HW_EVENT_1 0x1f
1630 #define FLT_REG_NPIV_CONF_0 0x29
1631 #define FLT_REG_NPIV_CONF_1 0x2a
1632 #define FLT_REG_GOLD_FW 0x2f
1633 #define FLT_REG_FCP_PRIO_0 0x87
1634 #define FLT_REG_FCP_PRIO_1 0x88
1635 #define FLT_REG_CNA_FW 0x97
1636 #define FLT_REG_BOOT_CODE_8044 0xA2
1637 #define FLT_REG_FCOE_FW 0xA4
1638 #define FLT_REG_FCOE_NVRAM_0 0xAA
1639 #define FLT_REG_FCOE_NVRAM_1 0xAC
1642 #define FLT_REG_IMG_PRI_27XX 0x95
1643 #define FLT_REG_IMG_SEC_27XX 0x96
1644 #define FLT_REG_FW_SEC_27XX 0x02
1645 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1646 #define FLT_REG_VPD_SEC_27XX_0 0x50
1647 #define FLT_REG_VPD_SEC_27XX_1 0x52
1648 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1649 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1652 #define FLT_REG_AUX_IMG_PRI_28XX 0x125
1653 #define FLT_REG_AUX_IMG_SEC_28XX 0x126
1654 #define FLT_REG_VPD_SEC_28XX_0 0x10C
1655 #define FLT_REG_VPD_SEC_28XX_1 0x10E
1656 #define FLT_REG_VPD_SEC_28XX_2 0x110
1657 #define FLT_REG_VPD_SEC_28XX_3 0x112
1658 #define FLT_REG_NVRAM_SEC_28XX_0 0x10D
1659 #define FLT_REG_NVRAM_SEC_28XX_1 0x10F
1660 #define FLT_REG_NVRAM_SEC_28XX_2 0x111
1661 #define FLT_REG_NVRAM_SEC_28XX_3 0x113
1662 #define FLT_REG_MPI_PRI_28XX 0xD3
1663 #define FLT_REG_MPI_SEC_28XX 0xF0
1664 #define FLT_REG_PEP_PRI_28XX 0xD1
1665 #define FLT_REG_PEP_SEC_28XX 0xF1
1681 struct qla_flt_region region[0];
1685 #define FLT_MAX_REGIONS 0xFF
1710 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1711 #define A84_PANIC_RECOVERY 0x1
1712 #define A84_OP_LOGIN_COMPLETE 0x2
1713 #define A84_DIAG_LOGIN_COMPLETE 0x3
1714 #define A84_GOLD_LOGIN_COMPLETE 0x4
1716 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1724 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1766 #define CS_VCS_CHIP_FAILURE 0x3
1767 #define CS_VCS_BAD_EXCHANGE 0x8
1768 #define CS_VCS_SEQ_COMPLETEi 0x40
1771 #define VFC_CHECKSUM_ERROR 0x1
1772 #define VFC_INVALID_LEN 0x2
1773 #define VFC_ALREADY_IN_PROGRESS 0x8
1783 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1793 #define ACO_DUMP_MEMORY 0x0
1794 #define ACO_LOAD_MEMORY 0x1
1795 #define ACO_CHANGE_CONFIG_PARAM 0x2
1796 #define ACO_REQUEST_INFO 0x3
1831 #define MBA_DCBX_START 0x8016
1832 #define MBA_DCBX_COMPLETE 0x8030
1833 #define MBA_FCF_CONF_ERR 0x8031
1834 #define MBA_DCBX_PARAM_UPDATE 0x8032
1835 #define MBA_IDC_COMPLETE 0x8100
1836 #define MBA_IDC_NOTIFY 0x8101
1837 #define MBA_IDC_TIME_EXT 0x8102
1839 #define MBC_IDC_ACK 0x101
1840 #define MBC_RESTART_MPI_FW 0x3d
1841 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1842 #define MBC_GET_XGMAC_STATS 0x7a
1843 #define MBC_GET_DCBX_PARAMS 0x51
1848 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1849 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1850 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1851 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1856 #define FAC_OPT_CMD_SUBCODE 0xff
1859 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1860 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1861 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1862 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1863 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1864 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1871 #define LR_DIST_NV_MASK 0xf
1875 #define FAC_SEMAPHORE_UNLOCK 0
1929 * BIT 0 = Enable spinup delay
1981 * BIT 0 = Selective Login
2020 /* Offset 406 (0x196) Enhanced Features
2021 * BIT 0 = Extended BB credits for LR
2023 * BIT 2-5 = Distance Support if BIT 0 is on
2095 * BIT 0-3 = Reserved
2108 * BIT 0 = Operation Mode bit 0
2126 * BIT 0-3 = Reserved
2127 * BIT 4 = FCP RSP Payload bit 0
2140 * BIT 28 = SPMA selection bit 0
2173 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2174 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
2175 #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
2176 #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
2180 #define QLFC_FCP_PRIO_DISABLE 0x0
2181 #define QLFC_FCP_PRIO_ENABLE 0x1
2182 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
2183 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
2188 #define FCP_PRIO_ENTRY_VALID 0x1
2189 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
2190 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
2191 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
2192 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
2193 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
2194 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
2195 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
2218 #define FCP_PRIO_ATTR_DISABLE 0x0
2219 #define FCP_PRIO_ATTR_ENABLE 0x1
2220 #define FCP_PRIO_ATTR_PERSIST 0x2
2230 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2231 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2234 #define FA_BOOT_CODE_ADDR_81 0x80000
2235 #define FA_RISC_CODE_ADDR_81 0xA0000
2236 #define FA_FW_AREA_ADDR_81 0xC0000
2237 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2238 #define FA_VPD0_ADDR_81 0xD0000
2239 #define FA_VPD1_ADDR_81 0xD0400
2240 #define FA_NVRAM0_ADDR_81 0xD0080
2241 #define FA_NVRAM1_ADDR_81 0xD0180
2242 #define FA_FEATURE_ADDR_81 0xD4000
2243 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2244 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2245 #define FA_HW_EVENT0_ADDR_81 0xDC000
2246 #define FA_HW_EVENT1_ADDR_81 0xDC400
2247 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2248 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2251 #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2252 #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2254 #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196