Lines Matching refs:pm8001_cw32
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); in pm80xx_bar4_shift()
141 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
285 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
362 pm8001_cw32(pm8001_ha, 0, in pm80xx_get_fatal_dump()
468 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, in pm80xx_get_non_fatal_dump()
1004 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
1521 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
1599 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); in pm80xx_chip_soft_rst()
1681 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); in pm80xx_hw_chip_rst()
1706 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1707 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1717 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); in pm80xx_chip_intx_interrupt_disable()
1732 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); in pm80xx_chip_interrupt_enable()
1753 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); in pm80xx_chip_interrupt_disable()