Lines Matching refs:pm8001_cw32
394 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); in pm8001_bar4_shift()
443 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
453 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
471 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); in mpi_set_phys_g3_with_ssc()
508 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
518 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
537 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
698 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); in pm8001_chip_init()
699 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); in pm8001_chip_init()
721 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
787 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, in soft_reset_ready_check()
789 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); in soft_reset_ready_check()
849 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); in pm8001_chip_soft_rst()
861 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); in pm8001_chip_soft_rst()
866 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
871 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); in pm8001_chip_soft_rst()
876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
881 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); in pm8001_chip_soft_rst()
890 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); in pm8001_chip_soft_rst()
918 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
930 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
941 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
952 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
974 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); in pm8001_chip_soft_rst()
990 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
998 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1009 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1036 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
1048 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); in pm8001_chip_soft_rst()
1055 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); in pm8001_chip_soft_rst()
1062 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); in pm8001_chip_soft_rst()
1079 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1118 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_soft_rst()
1119 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_soft_rst()
1165 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1173 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1221 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1222 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1232 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); in pm8001_chip_intx_interrupt_disable()
1250 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); in pm8001_chip_msix_interrupt_enable()
1252 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); in pm8001_chip_msix_interrupt_enable()
1268 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); in pm8001_chip_msix_interrupt_disable()
1381 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, in pm8001_mpi_build_cmd()
1418 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, in pm8001_mpi_msg_free_set()
1483 pm8001_cw32(pm8001_ha, in pm8001_mpi_msg_consume()
1496 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, in pm8001_mpi_msg_consume()