Lines Matching full:u
63 TWSI_RDY = (1U << 7), /* EEPROM interface ready */
64 TWSI_RD = (1U << 4), /* EEPROM read access */
71 INT_EN = (1U << 1), /* Global int enable */
72 HBA_RST = (1U << 0), /* HBA reset */
75 INT_XOR = (1U << 4), /* XOR engine event */
76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 SATA_TARGET = (1U << 16), /* port0 SATA target enable */
80 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
81 MODE_AUTO_DET_PORT6 = (1U << 14),
82 MODE_AUTO_DET_PORT5 = (1U << 13),
83 MODE_AUTO_DET_PORT4 = (1U << 12),
84 MODE_AUTO_DET_PORT3 = (1U << 11),
85 MODE_AUTO_DET_PORT2 = (1U << 10),
86 MODE_AUTO_DET_PORT1 = (1U << 9),
87 MODE_AUTO_DET_PORT0 = (1U << 8),
92 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
93 MODE_SAS_PORT6_MASK = (1U << 6),
94 MODE_SAS_PORT5_MASK = (1U << 5),
95 MODE_SAS_PORT4_MASK = (1U << 4),
96 MODE_SAS_PORT3_MASK = (1U << 3),
97 MODE_SAS_PORT2_MASK = (1U << 2),
98 MODE_SAS_PORT1_MASK = (1U << 1),
99 MODE_SAS_PORT0_MASK = (1U << 0),
111 TX_EN = (1U << 16), /* Enable TX */
115 RX_EN = (1U << 16), /* Enable RX */
119 COAL_EN = (1U << 16), /* Enable int coalescing */
122 CINT_I2C = (1U << 31), /* I2C event */
123 CINT_SW0 = (1U << 30), /* software event 0 */
124 CINT_SW1 = (1U << 29), /* software event 1 */
125 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
126 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
127 CINT_MEM = (1U << 26), /* int mem parity err */
128 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
129 CINT_NON_SPEC_NCQ_ERROR = (1U << 25), /* Non specific NCQ error */
130 CINT_SRS = (1U << 3), /* SRS event */
131 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
132 CINT_DONE = (1U << 0), /* cmd completion */
135 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
136 CINT_PORT = (1U << 8), /* port0 event */
149 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
152 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
162 RXQ_GOOD = (1U << 23), /* Response good */
163 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
164 RXQ_CMD_RX = (1U << 20), /* target cmd received */
165 RXQ_ATTN = (1U << 19), /* attention */
166 RXQ_RSP = (1U << 18), /* response frame xfer'd */
167 RXQ_ERR = (1U << 17), /* err info rec xfer'd */
168 RXQ_DONE = (1U << 16), /* cmd complete */
189 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
190 MCH_FBURST = (1U << 11), /* first burst (SSP) */
191 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
192 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
193 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
194 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
195 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
196 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
197 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
200 CCTL_RST = (1U << 5), /* port logic reset */
203 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
204 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
205 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
206 CCTL_ENDIAN_CMD = (1U << 0), /* command table */
209 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
210 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
211 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
212 PHY_RST = (1U << 0), /* phy reset */
213 PHY_READY_MASK = (1U << 20),
216 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
217 PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */
218 PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */
219 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
220 PHYEV_AN = (1U << 18), /* SATA async notification */
221 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
222 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
223 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
224 PHYEV_IU_BIG = (1U << 11), /* IU too long err */
225 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
226 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
227 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
228 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
229 PHYEV_PORT_SEL = (1U << 6), /* port selector present */
230 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
231 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
232 PHYEV_ID_FAIL = (1U << 3), /* identify failed */
233 PHYEV_ID_DONE = (1U << 2), /* identify done */
234 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
235 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
241 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
242 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
243 PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */
244 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
245 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
246 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
247 PCS_CMD_RST = (1U << 1), /* reset cmd issue */
248 PCS_CMD_EN = (1U << 0), /* enable cmd issue */
251 PORT_DEV_SSP_TRGT = (1U << 19),
252 PORT_DEV_SMP_TRGT = (1U << 18),
253 PORT_DEV_STP_TRGT = (1U << 17),
254 PORT_DEV_SSP_INIT = (1U << 11),
255 PORT_DEV_SMP_INIT = (1U << 10),
256 PORT_DEV_STP_INIT = (1U << 9),
265 PHY_RDY = (1U << 2),
266 PHY_DW_SYNC = (1U << 1),
267 PHY_OOB_DTCTD = (1U << 0),
271 PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
272 PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
273 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
274 PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
275 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
276 PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
277 PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
278 PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
279 PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
280 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
281 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
282 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
283 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
284 PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
379 MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
380 MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */
384 PHY_PLUG_EVENT = (3U),
385 PHY_PLUG_IN = (1U << 0), /* phy plug in */
386 PHY_PLUG_OUT = (1U << 1), /* phy plug out */
387 EXP_BRCT_CHG = (1U << 2), /* broadcast change */
391 PORT_TGT_MASK = (1U << 5),
392 PORT_INIT_PORT = (1U << 4),
393 PORT_TGT_PORT = (1U << 3),
395 PORT_TYPE_SAS = (1U << 1),
396 PORT_TYPE_SATA = (1U << 0),
422 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
423 CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
424 RSP_OVER = (1U << 29), /* rsp buffer overflow */
425 RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
426 UNK_FIS = (1U << 27), /* unknown FIS */
427 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
428 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
429 TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
430 R_ERR = (1U << 23), /* SATA returned R_ERR prim */
431 RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
432 XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
433 UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
434 DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
435 INTERLOCK = (1U << 15), /* interlock error */
436 NAK = (1U << 14), /* NAK rx'd */
437 ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
438 CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
439 OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
440 PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
441 NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
442 STP_RES_BSY = (1U << 8), /* STP resources busy */
443 BREAK = (1U << 7), /* break received */
444 BAD_DEST = (1U << 6), /* bad destination */
445 BAD_PROTO = (1U << 5), /* protocol not supported */
446 BAD_RATE = (1U << 4), /* cxn rate not supported */
447 WRONG_DEST = (1U << 3), /* wrong destination error */
448 CREDIT_TO = (1U << 2), /* credit timeout */
449 WDOG_TO = (1U << 1), /* watchdog timeout */
450 BUF_PAR = (1U << 0), /* buffer parity error */
454 SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
455 GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
456 APP_CHK_ERR = (1U << 13), /* Application Check error */
457 REF_CHK_ERR = (1U << 12), /* Reference Check Error */
458 USR_BLK_NM = (1U << 0), /* User Block Number */