Lines Matching refs:phy_id
35 static void set_phy_tuning(struct mvs_info *mvi, int phy_id, in set_phy_tuning() argument
80 mvs_write_port_vsr_addr(mvi, phy_id, setting_0); in set_phy_tuning()
81 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
86 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
89 mvs_write_port_vsr_addr(mvi, phy_id, setting_1); in set_phy_tuning()
90 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
93 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
97 static void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, in set_phy_ffe_tuning() argument
114 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); in set_phy_ffe_tuning()
115 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
123 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
129 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
130 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
135 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
142 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); in set_phy_ffe_tuning()
143 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
148 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
154 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
155 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
160 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
164 static void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) in set_phy_rate() argument
167 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in set_phy_rate()
168 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_rate()
200 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); in set_phy_rate()
203 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) in mvs_94xx_config_reg_from_hba() argument
206 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
208 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; in mvs_94xx_config_reg_from_hba()
209 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; in mvs_94xx_config_reg_from_hba()
210 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; in mvs_94xx_config_reg_from_hba()
213 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
218 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
219 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; in mvs_94xx_config_reg_from_hba()
225 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
226 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; in mvs_94xx_config_reg_from_hba()
231 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
234 mvi->hba_info_param.phy_rate[phy_id] = 0x2; in mvs_94xx_config_reg_from_hba()
236 set_phy_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
237 mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
238 set_phy_ffe_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
239 mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
240 set_phy_rate(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
241 mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
244 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) in mvs_94xx_enable_xmt() argument
250 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_94xx_enable_xmt()
254 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) in mvs_94xx_phy_reset() argument
259 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL); in mvs_94xx_phy_reset()
260 tmp = mvs_read_port_cfg_data(mvi, phy_id); in mvs_94xx_phy_reset()
261 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); in mvs_94xx_phy_reset()
262 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); in mvs_94xx_phy_reset()
265 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_94xx_phy_reset()
267 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
269 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
271 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
273 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
280 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
282 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
286 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_disable() argument
289 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_disable()
290 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_disable()
291 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); in mvs_94xx_phy_disable()
294 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_enable() argument
301 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
302 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); in mvs_94xx_phy_enable()
305 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); in mvs_94xx_phy_enable()
306 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); in mvs_94xx_phy_enable()
307 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
308 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); in mvs_94xx_phy_enable()
311 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_enable()
312 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_enable()
314 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); in mvs_94xx_phy_enable()
855 att_dev_info |= (u32)id->phy_id<<24; in mvs_94xx_make_dev_info()
894 static void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, in mvs_94xx_phy_set_link_rate() argument
900 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_set_link_rate()
907 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_set_link_rate()
908 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD); in mvs_94xx_phy_set_link_rate()