Lines Matching +full:0 +full:x0000001
37 #define LPFC_SKIP_UNREG_FCF 0
46 #define LPFC_HBA_HDWQ_MIN 0
51 #define LPFC_IRQ_CHANN_MIN 0
56 #define LPFC_FCP_MQ_THRESHOLD_MIN 0
65 #define LPFC_FCOE_FCF_DEF_INDEX 0
66 #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
67 #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
69 #define LPFC_FCOE_NULL_VID 0xFFF
70 #define LPFC_FCOE_IGNORE_VID 0xFFFF
73 #define LPFC_FCOE_FCF_MAC3 0xFF
74 #define LPFC_FCOE_FCF_MAC4 0xFF
75 #define LPFC_FCOE_FCF_MAC5 0xFE
76 #define LPFC_FCOE_FCF_MAP0 0x0E
77 #define LPFC_FCOE_FCF_MAP1 0xFC
78 #define LPFC_FCOE_FCF_MAP2 0x00
79 #define LPFC_FCOE_MAX_RCV_SIZE 0x800
80 #define LPFC_FCOE_FKA_ADV_PER 0
81 #define LPFC_FCOE_FIP_PRIORITY 0x80
84 ((fc_hdr)->fh_s_id[0] << 16 | \
89 ((fc_hdr)->fh_d_id[0] << 16 | \
94 ((fc_hdr)->fh_f_ctl[0] << 16 | \
103 #define INT_FW_UPGRADE 0
168 #define LPFC_EQ_INTERRUPT 0
229 #define LPFC_FIND_BY_EQ 0
232 #define LPFC_DB_RING_FORMAT 0x01
233 #define LPFC_DB_LIST_FORMAT 0x02
235 #define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
236 #define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
237 #define HBA_EQ_DELAY_CHK 0x2 /* EQ is a candidate for coalescing */
307 #define BOOT_ENABLE 0x01
308 #define RECORD_VALID 0x02
313 #define LPFC_FCF_ON_PRI_LIST 0x0001
314 #define LPFC_FCF_FLOGI_FAILED 0x0002
333 #define FCF_AVAILABLE 0x01 /* FCF available for discovery */
334 #define FCF_REGISTERED 0x02 /* FCF registered with FW */
335 #define FCF_SCAN_DONE 0x04 /* FCF table scan done */
336 #define FCF_IN_USE 0x08 /* Atleast one discovery completed */
337 #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
338 #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
339 #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
341 #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
342 #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
343 #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
360 #define LPFC_REGION23_LAST_REC 0xff
361 #define DRIVER_SPECIFIC_TYPE 0xA2
362 #define LINUX_DRIVER_ID 0x20
363 #define PORT_STE_TYPE 0x1
367 #define FCOE_PARAM_TYPE 0xA0
371 #define FIPP_VERSION 0x01
374 #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
376 #define FIPP_MODE_ON 0x1
377 #define FIPP_MODE_OFF 0x0
378 #define FIPP_VLAN_VALID 0x1
390 #define FCOE_CONN_TBL_TYPE 0xA1
397 #define FCFCNCT_VALID 0x0001
398 #define FCFCNCT_BOOT 0x0002
399 #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
400 #define FCFCNCT_FBNM_VALID 0x0008
401 #define FCFCNCT_SWNM_VALID 0x0010
402 #define FCFCNCT_VLAN_VALID 0x0020
403 #define FCFCNCT_AM_VALID 0x0040
404 #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
405 #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
458 #define SLI4_CT_RPI 0
506 #define lpfc_bbscn_min_SHIFT 0
507 #define lpfc_bbscn_min_MASK 0x0000000F
510 #define lpfc_bbscn_max_MASK 0x0000000F
513 #define lpfc_bbscn_def_MASK 0x0000000F
526 #define LPFC_SLI4_PROTO_FCOE 0x0000001
527 #define LPFC_SLI4_PROTO_FC 0x0000002
528 #define LPFC_SLI4_PROTO_NIC 0x0000004
529 #define LPFC_SLI4_PROTO_ISCSI 0x0000008
530 #define LPFC_SLI4_PROTO_RDMA 0x0000010
567 #define LPFC_CQ_4K_PAGE_SZ 0x1
568 #define LPFC_CQ_16K_PAGE_SZ 0x4
569 #define LPFC_WQ_4K_PAGE_SZ 0x1
570 #define LPFC_WQ_16K_PAGE_SZ 0x4
579 #define LPFC_LNK_DAT_INVAL 0
582 #define LPFC_LNK_GE 0x0 /* FCoE */
583 #define LPFC_LNK_FC 0x1 /* FC */
584 #define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */
599 #define LPFC_CPU_MAP_HYPER 0x1
600 #define LPFC_CPU_MAP_UNASSIGN 0x2
601 #define LPFC_CPU_FIRST_IRQ 0x4
603 #define LPFC_VECTOR_MAP_EMPTY 0xffff
730 while (spin_trylock_irqsave(lock, flag) == 0) { \
732 only_once = 0; \
740 while (spin_trylock(lock) == 0) { \
742 only_once = 0; \
777 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
784 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
788 #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
789 #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
791 #define SLIPORT_ERR2_REG_FW_RESTART 0x0
792 #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
793 #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
794 #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
795 #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
796 #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
797 #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
802 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
808 /* IF type 0, BAR 1 function CSR register memory map */
812 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
929 #define LPFC_SLI4_PPNAME_NON 0
949 #define lpfc_conf_trunk_port0_SHIFT 0
950 #define lpfc_conf_trunk_port0_MASK 0x1
953 #define lpfc_conf_trunk_port1_MASK 0x1
956 #define lpfc_conf_trunk_port2_MASK 0x1
959 #define lpfc_conf_trunk_port3_MASK 0x1
962 #define lpfc_conf_trunk_port0_nd_MASK 0x1
965 #define lpfc_conf_trunk_port1_nd_MASK 0x1
968 #define lpfc_conf_trunk_port2_nd_MASK 0x1
971 #define lpfc_conf_trunk_port3_nd_MASK 0x1