15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
38  * You should have received a copy of the GNU General Public License
115 #define ESAS2R_FWCOREDUMP_SZ        0x80000
117 #define ESAS2R_TARG_ID_INV          0xFFFF
120 #define ESAS2R_INT_DIS_MASK         0
134 /* macro to get the lowest nonzero bit of a value */
135 #define LOBIT(x) ((x) & (0 - (x)))
141 #define esas2r_read_register_dword(a, reg)                             \  argument
142 	readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)
144 #define esas2r_write_register_dword(a, reg, data)                      \  argument
145 	writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))
147 #define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r)  argument
153 #define esas2r_read_data_byte(a, reg)                                  \  argument
154 	readb((void __iomem *)a->data_window + (reg))
157 #define ATTO_VENDOR_ID          0x117C
158 #define ATTO_DID_INTEL_IOP348   0x002C
159 #define ATTO_DID_MV_88RC9580    0x0049
160 #define ATTO_DID_MV_88RC9580TS  0x0066
161 #define ATTO_DID_MV_88RC9580TSE 0x0067
162 #define ATTO_DID_MV_88RC9580TL  0x0068
165 #define ATTO_SSDID_TBT      0x4000
166 #define ATTO_TSSC_3808      0x4066
167 #define ATTO_TSSC_3808E     0x4067
168 #define ATTO_TLSH_1068      0x4068
169 #define ATTO_ESAS_R680      0x0049
170 #define ATTO_ESAS_R608      0x004A
171 #define ATTO_ESAS_R60F      0x004B
172 #define ATTO_ESAS_R6F0      0x004C
173 #define ATTO_ESAS_R644      0x004D
174 #define ATTO_ESAS_R648      0x004E
180 #define FBT_CPYR        0xAA00
181 #define FBT_SETUP       0xAA02
182 #define FBT_FLASH_VER   0xAA04
185 #define FLS_OFFSET_BOOT (u32)(0x00700000)
186 #define FLS_OFFSET_NVR  (u32)(0x007C0000)
189 #define FLS_BLOCK_SIZE  (u32)(0x00020000)
190 #define FI_NVR_2KB  0x0800
191 #define FI_NVR_8KB  0x2000
192 #define FM_BUF_SZ   0x800
198 #define MVR_FREY_B2     0xB2
201  * memory window definitions.  window 0 is the data window with definitions
205 #define MW_REG_WINDOW_SIZE      (u32)(0x00040000)
206 #define MW_REG_OFFSET_HWREG     (u32)(0x00000000)
207 #define MW_REG_OFFSET_PCI       (u32)(0x00008000)
209 #define MW_DATA_WINDOW_SIZE     (u32)(0x00020000)
210 #define MW_DATA_ADDR_SER_FLASH  (u32)(0xEC000000)
211 #define MW_DATA_ADDR_SRAM       (u32)(0xF4000000)
212 #define MW_DATA_ADDR_PAR_FLASH  (u32)(0xFC000000)
218 #define MU_IN_LIST_ADDR_LO      (u32)(0x00004000)
219 #define MU_IN_LIST_ADDR_HI      (u32)(0x00004004)
221 #define MU_IN_LIST_WRITE        (u32)(0x00004018)
222     #define MU_ILW_TOGGLE       (u32)(0x00004000)
224 #define MU_IN_LIST_READ         (u32)(0x0000401C)
225     #define MU_ILR_TOGGLE       (u32)(0x00004000)
226     #define MU_ILIC_LIST        (u32)(0x0000000F)
227     #define MU_ILIC_LIST_F0     (u32)(0x00000000)
228     #define MU_ILIC_DEST        (u32)(0x00000F00)
229     #define MU_ILIC_DEST_DDR    (u32)(0x00000200)
230 #define MU_IN_LIST_IFC_CONFIG   (u32)(0x00004028)
232 #define MU_IN_LIST_CONFIG       (u32)(0x0000402C)
233     #define MU_ILC_ENABLE       (u32)(0x00000001)
234     #define MU_ILC_ENTRY_MASK   (u32)(0x000000F0)
235     #define MU_ILC_ENTRY_4_DW   (u32)(0x00000020)
236     #define MU_ILC_DYNAMIC_SRC  (u32)(0x00008000)
237     #define MU_ILC_NUMBER_MASK  (u32)(0x7FFF0000)
240 #define MU_OUT_LIST_ADDR_LO     (u32)(0x00004050)
241 #define MU_OUT_LIST_ADDR_HI     (u32)(0x00004054)
243 #define MU_OUT_LIST_COPY_PTR_LO (u32)(0x00004058)
244 #define MU_OUT_LIST_COPY_PTR_HI (u32)(0x0000405C)
246 #define MU_OUT_LIST_WRITE       (u32)(0x00004068)
247     #define MU_OLW_TOGGLE       (u32)(0x00004000)
249 #define MU_OUT_LIST_COPY        (u32)(0x0000406C)
250     #define MU_OLC_TOGGLE       (u32)(0x00004000)
251     #define MU_OLC_WRT_PTR      (u32)(0x00003FFF)
253 #define MU_OUT_LIST_IFC_CONFIG  (u32)(0x00004078)
254     #define MU_OLIC_LIST        (u32)(0x0000000F)
255     #define MU_OLIC_LIST_F0     (u32)(0x00000000)
256     #define MU_OLIC_SOURCE      (u32)(0x00000F00)
257     #define MU_OLIC_SOURCE_DDR  (u32)(0x00000200)
259 #define MU_OUT_LIST_CONFIG      (u32)(0x0000407C)
260     #define MU_OLC_ENABLE       (u32)(0x00000001)
261     #define MU_OLC_ENTRY_MASK   (u32)(0x000000F0)
262     #define MU_OLC_ENTRY_4_DW   (u32)(0x00000020)
263     #define MU_OLC_NUMBER_MASK  (u32)(0x7FFF0000)
266 #define MU_OUT_LIST_INT_STAT    (u32)(0x00004088)
267     #define MU_OLIS_INT         (u32)(0x00000001)
269 #define MU_OUT_LIST_INT_MASK    (u32)(0x0000408C)
270     #define MU_OLIS_MASK        (u32)(0x00000001)
283 #define MU_CTL_STATUS_IN        (u32)(0x00010108)
284     #define MU_CTL_IN_FULL_RST  (u32)(0x00000020)
285 #define MU_CTL_STATUS_IN_B2     (u32)(0x00010130)
286     #define MU_CTL_IN_FULL_RST2 (u32)(0x80000000)
287 #define MU_DOORBELL_IN          (u32)(0x00010460)
288     #define DRBL_RESET_BUS      (u32)(0x00000002)
289     #define DRBL_PAUSE_AE       (u32)(0x00000004)
290     #define DRBL_RESUME_AE      (u32)(0x00000008)
291     #define DRBL_MSG_IFC_DOWN   (u32)(0x00000010)
292     #define DRBL_FLASH_REQ      (u32)(0x00000020)
293     #define DRBL_FLASH_DONE     (u32)(0x00000040)
294     #define DRBL_FORCE_INT      (u32)(0x00000080)
295     #define DRBL_MSG_IFC_INIT   (u32)(0x00000100)
296     #define DRBL_POWER_DOWN     (u32)(0x00000200)
297     #define DRBL_DRV_VER_1      (u32)(0x00010000)
299 #define MU_DOORBELL_IN_ENB      (u32)(0x00010464)
300 #define MU_DOORBELL_OUT         (u32)(0x00010480)
301  #define DRBL_PANIC_REASON_MASK (u32)(0x00F00000)
302     #define DRBL_UNUSED_HANDLER (u32)(0x00100000)
303     #define DRBL_UNDEF_INSTR    (u32)(0x00200000)
304     #define DRBL_PREFETCH_ABORT (u32)(0x00300000)
305     #define DRBL_DATA_ABORT     (u32)(0x00400000)
306     #define DRBL_JUMP_TO_ZERO   (u32)(0x00500000)
307   #define DRBL_FW_RESET         (u32)(0x00080000)
308   #define DRBL_FW_VER_MSK       (u32)(0x00070000)
309   #define DRBL_FW_VER_0         (u32)(0x00000000)
310   #define DRBL_FW_VER_1         (u32)(0x00010000)
312 #define MU_DOORBELL_OUT_ENB     (u32)(0x00010484)
313     #define DRBL_ENB_MASK       (u32)(0x00F803FF)
314 #define MU_INT_STATUS_OUT       (u32)(0x00010200)
315     #define MU_INTSTAT_POST_OUT (u32)(0x00000010)
316     #define MU_INTSTAT_DRBL_IN  (u32)(0x00000100)
317     #define MU_INTSTAT_DRBL     (u32)(0x00001000)
318     #define MU_INTSTAT_MASK     (u32)(0x00001010)
319 #define MU_INT_MASK_OUT         (u32)(0x0001020C)
322 #define MVR_PCI_WIN1_REMAP      (u32)(0x00008438)
323     #define MVRPW1R_ENABLE      (u32)(0x00000001)
332 	#define HWILSE_INTERFACE_F0  0x00000000
348 	#define CODE_TYPE_PC    0
352 	#define INDICATOR_LAST  0x80
381 	#define EFI_ROM_SIG     0x00000EF1
387 	#define EFI_MACHINE_IA32 0x014c
388 	#define EFI_MACHINE_IA64 0x0200
389 	#define EFI_MACHINE_X64  0x8664
390 	#define EFI_MACHINE_EBC  0x0EBC
392 	#define EFI_UNCOMPRESSED 0x0000
393 	#define EFI_COMPRESSED   0x0001
405 typedef void (*RQCALLBK)     (struct esas2r_adapter *a,
407 typedef bool (*RQBUILDSGL)   (struct esas2r_adapter *a,
412 	#define CH_IT_FW    0x00
413 	#define CH_IT_NVR   0x01
414 	#define CH_IT_BIOS  0x02
415 	#define CH_IT_MAC   0x03
416 	#define CH_IT_CFG   0x04
417 	#define CH_IT_EFI   0x05
419 	#define CH_STAT_PENDING 0xff
420 	#define CH_STAT_FAILED  0x00
421 	#define CH_STAT_SUCCESS 0x01
422 	#define CH_STAT_RETRY   0x02
423 	#define CH_STAT_INVALID 0x03
453 	#define FI_STAT_SUCCESS  0x00
454 	#define FI_STAT_FAILED   0x01
455 	#define FI_STAT_REBOOT   0x02
456 	#define FI_STAT_ADAPTYP  0x03
457 	#define FI_STAT_INVALID  0x04
458 	#define FI_STAT_CHKSUM   0x05
459 	#define FI_STAT_LENGTH   0x06
460 	#define FI_STAT_UNKNOWN  0x07
461 	#define FI_STAT_IMG_VER  0x08
462 	#define FI_STAT_BUSY     0x09
463 	#define FI_STAT_DUAL     0x0A
464 	#define FI_STAT_MISSING  0x0B
465 	#define FI_STAT_UNSUPP   0x0C
466 	#define FI_STAT_ERASE    0x0D
467 	#define FI_STAT_FLASH    0x0E
468 	#define FI_STAT_DEGRADED 0x0F
470 	#define FI_AT_UNKNWN    0xFF
471 	#define FI_AT_SUN_LAKE  0x0B
472 	#define FI_AT_MV_9580   0x0F
474 	#define FI_ACT_DOWN     0x00
475 	#define FI_ACT_UP       0x01
476 	#define FI_ACT_UPSZ     0x02
477 	#define FI_ACT_MAX      0x02
478 	#define FI_ACT_DOWN1    0x80
483 	#define FI_FLG_NVR_DEF  0x0001
494 	#define ESAS2R_FS_CMD_ERASE    0
509 	#define ESAS2R_FS_VER      0
526 	#define SASNVR_VERSION_0    0x00
529 	#define SASNVR_CKSUM_SEED   0x5A
532 	#define SASNVR_PCILAT_DIS   0x00
533 	#define SASNVR_PCILAT_MIN   0x10
534 	#define SASNVR_PCILAT_MAX   0xF8
536 	#define SASNVR1_BOOT_DRVR   0x01
537 	#define SASNVR1_BOOT_SCAN   0x02
538 	#define SASNVR1_DIS_PCI_MWI 0x04
539 	#define SASNVR1_FORCE_ORD_Q 0x08
540 	#define SASNVR1_CACHELINE_0 0x10
541 	#define SASNVR1_DIS_DEVSORT 0x20
542 	#define SASNVR1_PWR_MGT_EN  0x40
543 	#define SASNVR1_WIDEPORT    0x80
545 	#define SASNVR2_SINGLE_BUS  0x01
546 	#define SASNVR2_SLOT_BIND   0x02
547 	#define SASNVR2_EXP_PROG    0x04
548 	#define SASNVR2_CMDTHR_LUN  0x08
549 	#define SASNVR2_HEARTBEAT   0x10
550 	#define SASNVR2_INT_CONNECT 0x20
551 	#define SASNVR2_SW_MUX_CTRL 0x40
552 	#define SASNVR2_DISABLE_NCQ 0x80
554 	#define SASNVR_COAL_DIS     0x00
555 	#define SASNVR_COAL_LOW     0x01
556 	#define SASNVR_COAL_MED     0x02
557 	#define SASNVR_COAL_HI      0x03
559 	#define SASNVR_CMDTHR_NONE  0x00
563 	#define SASNVR_SPINUP_MAX   0x14
567 	#define SASNVR_SPEED_AUTO   0x00
568 	#define SASNVR_SPEED_1_5GB  0x01
569 	#define SASNVR_SPEED_3GB    0x02
570 	#define SASNVR_SPEED_6GB    0x03
571 	#define SASNVR_SPEED_12GB   0x04
573 	#define SASNVR_MUX_DISABLED 0x00
574 	#define SASNVR_MUX_1_5GB    0x01
575 	#define SASNVR_MUX_3GB      0x02
576 	#define SASNVR_MUX_6GB      0x03
578 	#define SASNVR_PHF_DISABLED 0x01
579 	#define SASNVR_PHF_RD_ONLY  0x02
581 	#define SASNVR_SORT_SAS_ADDR    0x00
582 	#define SASNVR_SORT_H308_CONN   0x01
583 	#define SASNVR_SORT_PHY_ID      0x02
584 	#define SASNVR_SORT_SLOT_ID     0x03
589 	#define SASNVR_PTI_DISABLED     0xFF
591 	#define SASNVR_VSMH_DISABLED    0x00
593 	#define SASNVR_RWM_DEFAULT      0x00
595 	u8 reserved[0xA1];
628 	#define TF_PASS_THRU    0x01
629 	#define TF_USED         0x02
633 #define TS_NOT_PRESENT      0x00
634 #define TS_PRESENT          0x05
635 #define TS_LUN_CHANGE       0x06
636 #define TS_INVALID          0xFF
661 	#define RQ_TIMEOUT_S1     0xFFFFFFFF
662 	#define RQ_TIMEOUT_S2     0xFFFFFFFE
663 	#define RQ_MAX_TIMEOUT    0xFFFFFFFD
666 	#define RT_INI_REQ          0x01
667 	#define RT_DISC_REQ         0x02
674 	#define RF_1ST_IBLK_BASE    0x04
675 	#define RF_FAILURE_OK       0x08
678 	#define RQ_SIZE_DEFAULT   0
697 	#define     FMTSK_ERASE_BOOT    0
717 	#define DCDE_DEV_CHANGE     0x01
718 	#define DCDE_DEV_SCAN       0x02
720 	#define DCS_DEV_RMV         0x00
721 	#define DCS_DEV_ADD         0x01
722 	#define DCS_BLOCK_DEV_SCAN  0x02
723 	#define DCS_RAID_GRP_INFO   0x03
724 	#define DCS_PART_INFO       0x04
725 	#define DCS_PT_DEV_INFO     0x05
726 	#define DCS_PT_DEV_ADDR     0x06
727 	#define DCS_DISC_DONE       0xFF
729 	#define DCF_DEV_CHANGE      0x0001
730 	#define DCF_DEV_SCAN        0x0002
731 	#define DCF_POLLED          0x8000
766 #define ESAS2R_VDA_EVENT_SIG  0x4154544F
776 	struct esas2r_adapter *a;  member
803 	#define AF_PORT_CHANGE      0
830 	#define AF2_SERIAL_FLASH    0
919 #define VDA_MAX_BUFFER_SIZE  (0x40000 + VDA_BUFFER_HEADER_SZ)
940 #define INTR_MODE_LEGACY 0
966 int esas2r_write_params(struct esas2r_adapter *a, struct esas2r_request *rq,
970 u8 handle_hba_ioctl(struct esas2r_adapter *a,
986 int esas2r_read_fw(struct esas2r_adapter *a, char *buf, long off, int count);
987 int esas2r_write_fw(struct esas2r_adapter *a, const char *buf, long off,
989 int esas2r_read_vda(struct esas2r_adapter *a, char *buf, long off, int count);
990 int esas2r_write_vda(struct esas2r_adapter *a, const char *buf, long off,
992 int esas2r_read_fs(struct esas2r_adapter *a, char *buf, long off, int count);
993 int esas2r_write_fs(struct esas2r_adapter *a, const char *buf, long off,
998 void esas2r_kickoff_timer(struct esas2r_adapter *a);
1001 void esas2r_fw_event_off(struct esas2r_adapter *a);
1002 void esas2r_fw_event_on(struct esas2r_adapter *a);
1003 bool esas2r_nvram_write(struct esas2r_adapter *a, struct esas2r_request *rq,
1005 void esas2r_nvram_get_defaults(struct esas2r_adapter *a,
1007 void esas2r_complete_request_cb(struct esas2r_adapter *a,
1009 void esas2r_reset_detected(struct esas2r_adapter *a);
1014 void esas2r_free_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1015 struct esas2r_request *esas2r_alloc_request(struct esas2r_adapter *a);
1016 u32 esas2r_get_uncached_size(struct esas2r_adapter *a);
1017 bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
1019 bool esas2r_check_adapter(struct esas2r_adapter *a);
1020 bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll);
1021 void esas2r_start_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1022 bool esas2r_send_task_mgmt(struct esas2r_adapter *a,
1024 void esas2r_do_tasklet_tasks(struct esas2r_adapter *a);
1025 void esas2r_adapter_interrupt(struct esas2r_adapter *a);
1026 void esas2r_do_deferred_processes(struct esas2r_adapter *a);
1027 void esas2r_reset_bus(struct esas2r_adapter *a);
1028 void esas2r_reset_adapter(struct esas2r_adapter *a);
1029 void esas2r_timer_tick(struct esas2r_adapter *a);
1030 const char *esas2r_get_model_name(struct esas2r_adapter *a);
1031 const char *esas2r_get_model_name_short(struct esas2r_adapter *a);
1032 u32 esas2r_stall_execution(struct esas2r_adapter *a, u32 start_time,
1034 void esas2r_build_flash_req(struct esas2r_adapter *a,
1040 void esas2r_build_mgt_req(struct esas2r_adapter *a,
1047 void esas2r_build_ae_req(struct esas2r_adapter *a, struct esas2r_request *rq);
1048 void esas2r_build_cli_req(struct esas2r_adapter *a,
1052 void esas2r_build_ioctl_req(struct esas2r_adapter *a,
1056 void esas2r_build_cfg_req(struct esas2r_adapter *a,
1061 void esas2r_power_down(struct esas2r_adapter *a);
1062 bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll);
1063 void esas2r_wait_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1064 u32 esas2r_map_data_window(struct esas2r_adapter *a, u32 addr_lo);
1065 bool esas2r_process_fs_ioctl(struct esas2r_adapter *a,
1069 bool esas2r_read_flash_block(struct esas2r_adapter *a, void *to, u32 from,
1071 bool esas2r_read_mem_block(struct esas2r_adapter *a, void *to, u32 from,
1073 bool esas2r_fm_api(struct esas2r_adapter *a, struct esas2r_flash_img *fi,
1075 void esas2r_force_interrupt(struct esas2r_adapter *a);
1076 void esas2r_local_start_request(struct esas2r_adapter *a,
1078 void esas2r_process_adapter_reset(struct esas2r_adapter *a);
1079 void esas2r_complete_request(struct esas2r_adapter *a,
1081 void esas2r_dummy_complete(struct esas2r_adapter *a,
1083 void esas2r_ae_complete(struct esas2r_adapter *a, struct esas2r_request *rq);
1084 void esas2r_start_vda_request(struct esas2r_adapter *a,
1086 bool esas2r_read_flash_rev(struct esas2r_adapter *a);
1087 bool esas2r_read_image_type(struct esas2r_adapter *a);
1088 bool esas2r_nvram_read_direct(struct esas2r_adapter *a);
1089 bool esas2r_nvram_validate(struct esas2r_adapter *a);
1090 void esas2r_nvram_set_defaults(struct esas2r_adapter *a);
1091 bool esas2r_print_flash_rev(struct esas2r_adapter *a);
1092 void esas2r_send_reset_ae(struct esas2r_adapter *a, bool pwr_mgt);
1093 bool esas2r_init_msgs(struct esas2r_adapter *a);
1094 bool esas2r_is_adapter_present(struct esas2r_adapter *a);
1098 void esas2r_reset_chip(struct esas2r_adapter *a);
1099 void esas2r_log_request_failure(struct esas2r_adapter *a,
1101 void esas2r_polled_interrupt(struct esas2r_adapter *a);
1102 bool esas2r_ioreq_aborted(struct esas2r_adapter *a, struct esas2r_request *rq,
1104 bool esas2r_build_sg_list_sge(struct esas2r_adapter *a,
1106 bool esas2r_build_sg_list_prd(struct esas2r_adapter *a,
1108 void esas2r_targ_db_initialize(struct esas2r_adapter *a);
1109 void esas2r_targ_db_remove_all(struct esas2r_adapter *a, bool notify);
1110 void esas2r_targ_db_report_changes(struct esas2r_adapter *a);
1111 struct esas2r_target *esas2r_targ_db_add_raid(struct esas2r_adapter *a,
1113 struct esas2r_target *esas2r_targ_db_add_pthru(struct esas2r_adapter *a,
1117 void esas2r_targ_db_remove(struct esas2r_adapter *a, struct esas2r_target *t);
1118 struct esas2r_target *esas2r_targ_db_find_by_sas_addr(struct esas2r_adapter *a,
1120 struct esas2r_target *esas2r_targ_db_find_by_ident(struct esas2r_adapter *a,
1123 u16 esas2r_targ_db_find_next_present(struct esas2r_adapter *a, u16 target_id);
1124 struct esas2r_target *esas2r_targ_db_find_by_virt_id(struct esas2r_adapter *a,
1126 u16 esas2r_targ_db_get_tgt_cnt(struct esas2r_adapter *a);
1127 void esas2r_disc_initialize(struct esas2r_adapter *a);
1128 void esas2r_disc_start_waiting(struct esas2r_adapter *a);
1129 void esas2r_disc_check_for_work(struct esas2r_adapter *a);
1130 void esas2r_disc_check_complete(struct esas2r_adapter *a);
1131 void esas2r_disc_queue_event(struct esas2r_adapter *a, u8 disc_evt);
1132 bool esas2r_disc_start_port(struct esas2r_adapter *a);
1133 void esas2r_disc_local_start_request(struct esas2r_adapter *a,
1135 bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str);
1136 bool esas2r_process_vda_ioctl(struct esas2r_adapter *a,
1140 void esas2r_queue_fw_event(struct esas2r_adapter *a,
1147 /* Allocate a chip scatter/gather list entry */
1148 static inline struct esas2r_mem_desc *esas2r_alloc_sgl(struct esas2r_adapter *a)  in esas2r_alloc_sgl()  argument
1154 	spin_lock_irqsave(&a->sg_list_lock, flags);  in esas2r_alloc_sgl()
1155 	if (likely(!list_empty(&a->free_sg_list_head))) {  in esas2r_alloc_sgl()
1156 		sgl = a->free_sg_list_head.next;  in esas2r_alloc_sgl()
1160 	spin_unlock_irqrestore(&a->sg_list_lock, flags);  in esas2r_alloc_sgl()
1165 /* Initialize a scatter/gather context */
1167 				   struct esas2r_adapter *a,  in esas2r_sgc_init()  argument
1171 	sgc->adapter = a;  in esas2r_sgc_init()
1192 			sgc->sge.a64.curr = &rq->vrq->scsi.u.sge[0];  in esas2r_sgc_init()
1200 					  struct esas2r_adapter *a)  in esas2r_rq_init_request()  argument
1208 	rq->flags = 0;  in esas2r_rq_init_request()
1209 	rq->timeout = 0;  in esas2r_rq_init_request()
1214 	rq->func_rsp.dwords[0] = 0;  in esas2r_rq_init_request()
1215 	rq->func_rsp.dwords[1] = 0;  in esas2r_rq_init_request()
1221 	 * time through sets a smaller request size.  if this is not modified  in esas2r_rq_init_request()
1228 	if (a->req_table[LOWORD(vrq->scsi.handle)]) {  in esas2r_rq_init_request()
1235 	a->req_table[LOWORD(vrq->scsi.handle)] = rq;  in esas2r_rq_init_request()
1238 	 * add a reference number to the handle to make it unique (until it  in esas2r_rq_init_request()
1241 	vrq->scsi.handle = (a->cmd_ref_no++ << 16) | (u16)vrq->scsi.handle;  in esas2r_rq_init_request()
1244 	 * the following formats a SCSI request.  the caller can override as  in esas2r_rq_init_request()
1252 	vrq->scsi.sg_list_offset = 0;  in esas2r_rq_init_request()
1253 	vrq->scsi.chain_offset = 0;  in esas2r_rq_init_request()
1254 	vrq->scsi.flags = 0;  in esas2r_rq_init_request()
1255 	vrq->scsi.reserved = 0;  in esas2r_rq_init_request()
1264 					   struct esas2r_adapter *a)  in esas2r_rq_free_sg_lists()  argument
1271 	spin_lock_irqsave(&a->sg_list_lock, flags);  in esas2r_rq_free_sg_lists()
1272 	list_splice_tail_init(&rq->sg_table_head, &a->free_sg_list_head);  in esas2r_rq_free_sg_lists()
1273 	spin_unlock_irqrestore(&a->sg_list_lock, flags);  in esas2r_rq_free_sg_lists()
1277 					     struct esas2r_adapter *a)  in esas2r_rq_destroy_request()  argument
1280 	esas2r_rq_free_sg_lists(rq, a);  in esas2r_rq_destroy_request()
1281 	a->req_table[LOWORD(rq->vrq->scsi.handle)] = NULL;  in esas2r_rq_destroy_request()
1285 static inline bool esas2r_is_tasklet_pending(struct esas2r_adapter *a)  in esas2r_is_tasklet_pending()  argument
1288 	return test_bit(AF_BUSRST_NEEDED, &a->flags) ||  in esas2r_is_tasklet_pending()
1289 	       test_bit(AF_BUSRST_DETECTED, &a->flags) ||  in esas2r_is_tasklet_pending()
1290 	       test_bit(AF_CHPRST_NEEDED, &a->flags) ||  in esas2r_is_tasklet_pending()
1291 	       test_bit(AF_CHPRST_DETECTED, &a->flags) ||  in esas2r_is_tasklet_pending()
1292 	       test_bit(AF_PORT_CHANGE, &a->flags);  in esas2r_is_tasklet_pending()
1302 static inline bool esas2r_build_sg_list(struct esas2r_adapter *a,  in esas2r_build_sg_list()  argument
1306 	if (unlikely(le32_to_cpu(rq->vrq->scsi.length) == 0))  in esas2r_build_sg_list()
1309 	return (*a->build_sgl)(a, sgc);  in esas2r_build_sg_list()
1312 static inline void esas2r_disable_chip_interrupts(struct esas2r_adapter *a)  in esas2r_disable_chip_interrupts()  argument
1314 	if (atomic_inc_return(&a->dis_ints_cnt) == 1)  in esas2r_disable_chip_interrupts()
1315 		esas2r_write_register_dword(a, MU_INT_MASK_OUT,  in esas2r_disable_chip_interrupts()
1319 static inline void esas2r_enable_chip_interrupts(struct esas2r_adapter *a)  in esas2r_enable_chip_interrupts()  argument
1321 	if (atomic_dec_return(&a->dis_ints_cnt) == 0)  in esas2r_enable_chip_interrupts()
1322 		esas2r_write_register_dword(a, MU_INT_MASK_OUT,  in esas2r_enable_chip_interrupts()
1326 /* Schedule a TASKLET to perform non-interrupt tasks that may require delays
1329 static inline void esas2r_schedule_tasklet(struct esas2r_adapter *a)  in esas2r_schedule_tasklet()  argument
1332 	if (!test_and_set_bit(AF_TASKLET_SCHEDULED, &a->flags))  in esas2r_schedule_tasklet()
1333 		tasklet_hi_schedule(&a->tasklet);  in esas2r_schedule_tasklet()
1336 static inline void esas2r_enable_heartbeat(struct esas2r_adapter *a)  in esas2r_enable_heartbeat()  argument
1338 	if (!test_bit(AF_DEGRADED_MODE, &a->flags) &&  in esas2r_enable_heartbeat()
1339 	    !test_bit(AF_CHPRST_PENDING, &a->flags) &&  in esas2r_enable_heartbeat()
1340 	    (a->nvram->options2 & SASNVR2_HEARTBEAT))  in esas2r_enable_heartbeat()
1341 		set_bit(AF_HEARTBEAT_ENB, &a->flags);  in esas2r_enable_heartbeat()
1343 		clear_bit(AF_HEARTBEAT_ENB, &a->flags);  in esas2r_enable_heartbeat()
1346 static inline void esas2r_disable_heartbeat(struct esas2r_adapter *a)  in esas2r_disable_heartbeat()  argument
1348 	clear_bit(AF_HEARTBEAT_ENB, &a->flags);  in esas2r_disable_heartbeat()
1349 	clear_bit(AF_HEARTBEAT, &a->flags);  in esas2r_disable_heartbeat()
1355 static inline void esas2r_local_reset_adapter(struct esas2r_adapter *a)  in esas2r_local_reset_adapter()  argument
1357 	esas2r_disable_heartbeat(a);  in esas2r_local_reset_adapter()
1359 	set_bit(AF_CHPRST_NEEDED, &a->flags);  in esas2r_local_reset_adapter()
1360 	set_bit(AF_CHPRST_PENDING, &a->flags);  in esas2r_local_reset_adapter()
1361 	set_bit(AF_DISC_PENDING, &a->flags);  in esas2r_local_reset_adapter()
1365 static inline bool esas2r_adapter_interrupt_pending(struct esas2r_adapter *a)  in esas2r_adapter_interrupt_pending()  argument
1369 	if (a->int_mask == 0)  in esas2r_adapter_interrupt_pending()
1372 	intstat = esas2r_read_register_dword(a, MU_INT_STATUS_OUT);  in esas2r_adapter_interrupt_pending()
1374 	if ((intstat & a->int_mask) == 0)  in esas2r_adapter_interrupt_pending()
1377 	esas2r_disable_chip_interrupts(a);  in esas2r_adapter_interrupt_pending()
1379 	a->int_stat = intstat;  in esas2r_adapter_interrupt_pending()
1380 	a->int_mask = 0;  in esas2r_adapter_interrupt_pending()
1386 				     struct esas2r_adapter *a)  in esas2r_targ_get_id()  argument
1388 	return (u16)(uintptr_t)(t - a->targetdb);  in esas2r_targ_get_id()
1392 static inline void esas2r_start_ae_request(struct esas2r_adapter *a,  in esas2r_start_ae_request()  argument
1397 	esas2r_build_ae_req(a, rq);  in esas2r_start_ae_request()
1399 	spin_lock_irqsave(&a->queue_lock, flags);  in esas2r_start_ae_request()
1400 	esas2r_start_vda_request(a, rq);  in esas2r_start_ae_request()
1401 	spin_unlock_irqrestore(&a->queue_lock, flags);  in esas2r_start_ae_request()
1404 static inline void esas2r_comp_list_drain(struct esas2r_adapter *a,  in esas2r_comp_list_drain()  argument
1413 		esas2r_complete_request(a, rq);  in esas2r_comp_list_drain()