Lines Matching +full:0 +full:x26000
68 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
72 #define PCI_DEVICE_ID_ARECA_1880 0x1880
75 #define PCI_DEVICE_ID_ARECA_1214 0x1214
78 #define PCI_DEVICE_ID_ARECA_1203 0x1203
81 #define PCI_DEVICE_ID_ARECA_1884 0x1884
83 #define PCI_DEVICE_ID_ARECA_1886 0x188A
91 #define ARC_SUCCESS 0
99 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
126 #define ARCMSR_MESSAGE_FAIL 0x0001
128 #define ARECA_SATA_RAID 0x90000000
130 #define FUNCTION_READ_RQBUFFER 0x0801
131 #define FUNCTION_WRITE_WQBUFFER 0x0802
132 #define FUNCTION_CLEAR_RQBUFFER 0x0803
133 #define FUNCTION_CLEAR_WQBUFFER 0x0804
134 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
135 #define FUNCTION_RETURN_CODE_3F 0x0806
136 #define FUNCTION_SAY_HELLO 0x0807
137 #define FUNCTION_SAY_GOODBYE 0x0808
138 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
139 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A
140 #define FUNCTION_HARDWARE_RESET 0x080B
161 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
162 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
163 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
164 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
171 #define IS_SG64_ADDR 0x01000000 /* bit24 */
200 uint32_t signature; /*0, 00-03*/
214 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
215 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
217 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
218 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
219 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
220 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
221 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
222 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
223 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
224 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
225 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
227 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
228 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
229 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
230 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
232 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
233 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
234 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
235 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
236 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
238 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
240 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
242 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
243 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
252 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400
253 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
255 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408
256 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
258 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870
259 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
261 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878
262 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
265 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
267 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
268 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
269 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
271 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
272 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
273 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
275 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
277 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
279 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
281 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
283 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
285 #define ARCMSR_MESSAGE_START_BGRB 0x00060008
286 #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
287 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
288 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
289 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
291 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
293 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
295 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
296 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
297 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
298 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
302 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
304 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
306 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
318 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes t…
319 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Door…
320 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List F…
321 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
323 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
328 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
335 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
341 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
347 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
348 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
349 /*inbound message 0 ready*/
350 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
352 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
353 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
355 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
356 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
358 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
359 /*outbound message 0 ready*/
360 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
362 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
364 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
370 #define ARCMSR_ARC1214_CHIP_ID 0x00004
371 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
372 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
373 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
374 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108
375 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
376 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
377 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
378 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
379 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
380 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
381 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
382 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
383 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
384 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
385 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
386 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
387 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
388 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
389 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
390 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
391 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
392 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
393 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
394 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
395 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
397 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
398 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
400 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
401 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
403 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
404 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
405 /*inbound message 0 ready*/
406 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
408 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
409 /*outbound message 0 ready*/
410 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
413 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
414 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
420 #define ARCMSR_SIGNATURE_1884 0x188417D3
422 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
423 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
424 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
426 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
427 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
428 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
430 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000
432 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
433 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
434 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009
437 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
438 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
439 #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080
446 #define ARCMSR_SIGNATURE_1886 0x188617D3
449 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
450 //set host rw buffer physical address at inbound message 0, 1 (low,high)
451 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
452 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
453 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
457 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
469 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
470 #define ARCMSR_CDB_FLAG_BIOS 0x02
471 #define ARCMSR_CDB_FLAG_WRITE 0x04
472 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
473 #define ARCMSR_CDB_FLAG_HEADQ 0x08
474 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
481 #define ARCMSR_DEV_CHECK_CONDITION 0x02
482 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
483 #define ARCMSR_DEV_ABORTED 0xF1
484 #define ARCMSR_DEV_INIT_FAIL 0xF2
517 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
518 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
519 uint32_t reserved5[32]; /*0E80 0EFF 32*/
520 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
521 uint32_t reserved6[32]; /*0F80 0FFF 32*/
636 u32 __iomem *chip_id; /* 0x00004 */
637 u32 __iomem *cpu_mem_config; /* 0x00008 */
638 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
639 u32 __iomem *sample_at_reset; /* 0x00100 */
640 u32 __iomem *reset_request; /* 0x00108 */
641 u32 __iomem *host_int_status; /* 0x00200 */
642 u32 __iomem *pcief0_int_enable; /* 0x0020C */
643 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
644 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
645 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
646 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
647 u32 __iomem *inbound_doorbell; /* 0x00460 */
648 u32 __iomem *outbound_doorbell; /* 0x00480 */
649 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
650 u32 __iomem *inboundlist_base_low; /* 0x01000 */
651 u32 __iomem *inboundlist_base_high; /* 0x01004 */
652 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
653 u32 __iomem *outboundlist_base_low; /* 0x01060 */
654 u32 __iomem *outboundlist_base_high; /* 0x01064 */
655 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
656 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
657 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
658 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
659 u32 __iomem *message_wbuffer; /* 0x2000 */
660 u32 __iomem *message_rbuffer; /* 0x2100 */
661 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
816 uint16_t cmdLMID; // reserved (0)
817 uint16_t cmdFlag2; // reserved (0)
827 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
828 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
829 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
830 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
831 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
832 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */
859 //0x000 - COMPORT_IN (Host sent to ROC)
861 //0x100 - COMPORT_OUT (ROC sent to Host)
863 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
867 #define ACB_F_SCSISTOPADAPTER 0x0001
868 #define ACB_F_MSG_STOP_BGRB 0x0002
870 #define ACB_F_MSG_START_BGRB 0x0004
872 #define ACB_F_IOPDATA_OVERFLOW 0x0008
874 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
876 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
878 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
879 #define ACB_F_BUS_RESET 0x0080
881 #define ACB_F_IOP_INITED 0x0100
883 #define ACB_F_ABORT 0x0200
884 #define ACB_F_FIRMWARE_TRAP 0x0400
885 #define ACB_F_ADAPTER_REMOVED 0x0800
886 #define ACB_F_MSG_GET_CONFIG 0x1000
917 #define ARECA_RAID_GONE 0x55
918 #define ARECA_RAID_GOOD 0xaa
933 #define FW_NORMAL 0x0000
934 #define FW_BOG 0x0001
935 #define FW_DEADLOCK 0x0010
962 #define CCB_FLAG_READ 0x0000
963 #define CCB_FLAG_WRITE 0x0001
964 #define CCB_FLAG_ERROR 0x0002
965 #define CCB_FLAG_FLUSHCACHE 0x0004
966 #define CCB_FLAG_MASTER_ABORTED 0x0008
968 #define ARCMSR_CCB_DONE 0x0000
969 #define ARCMSR_CCB_START 0x55AA
970 #define ARCMSR_CCB_ABORTED 0xAA55
971 #define ARCMSR_CCB_ILLEGAL 0xFFFF
991 #define SCSI_SENSE_CURRENT_ERRORS 0x70
992 #define SCSI_SENSE_DEFERRED_ERRORS 0x71
1013 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
1014 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
1015 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
1016 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
1017 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
1018 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
1030 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
1031 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
1032 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
1033 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
1034 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
1035 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
1036 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F