Lines Matching +full:ipq8074 +full:- +full:wcss +full:- +full:pil
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Linaro Ltd.
5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
100 static int q6v5_wcss_reset(struct q6v5_wcss *wcss) in q6v5_wcss_reset() argument
107 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
109 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
117 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
121 dev_err(wcss->dev, in q6v5_wcss_reset()
126 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
128 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
133 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
136 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
138 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
142 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
145 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
146 for (i = MEM_BANKS; i >= 0; i--) { in q6v5_wcss_reset()
148 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
154 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
158 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
160 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
164 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
167 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
169 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
172 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
174 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
177 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
179 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
186 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_start() local
189 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_wcss_start()
191 /* Release Q6 and WCSS reset */ in q6v5_wcss_start()
192 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_start()
194 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_wcss_start()
198 ret = reset_control_deassert(wcss->wcss_q6_reset); in q6v5_wcss_start()
200 dev_err(wcss->dev, "wcss_q6_reset failed\n"); in q6v5_wcss_start()
204 /* Lithium configuration - clock gating and bus arbitration */ in q6v5_wcss_start()
205 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
206 wcss->halt_nc + TCSR_GLOBAL_CFG0, in q6v5_wcss_start()
212 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
213 wcss->halt_nc + TCSR_GLOBAL_CFG1, in q6v5_wcss_start()
219 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_wcss_start()
221 ret = q6v5_wcss_reset(wcss); in q6v5_wcss_start()
225 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_wcss_start()
226 if (ret == -ETIMEDOUT) in q6v5_wcss_start()
227 dev_err(wcss->dev, "start timed out\n"); in q6v5_wcss_start()
232 reset_control_assert(wcss->wcss_q6_reset); in q6v5_wcss_start()
235 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_start()
240 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, in q6v5_wcss_halt_axi_port() argument
268 dev_err(wcss->dev, "port failed halt\n"); in q6v5_wcss_halt_axi_port()
274 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) in q6v5_wcss_powerdown() argument
279 /* 1 - Assert WCSS/Q6 HALTREQ */ in q6v5_wcss_powerdown()
280 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_wcss_powerdown()
282 /* 2 - Enable WCSSAON_CONFIG */ in q6v5_wcss_powerdown()
283 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
285 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
287 /* 3 - Set SSCAON_CONFIG */ in q6v5_wcss_powerdown()
290 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
292 /* 4 - SSCAON_CONFIG 1 */ in q6v5_wcss_powerdown()
294 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
296 /* 5 - wait for SSCAON_STATUS */ in q6v5_wcss_powerdown()
297 ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, in q6v5_wcss_powerdown()
301 dev_err(wcss->dev, in q6v5_wcss_powerdown()
306 /* 6 - De-assert WCSS_AON reset */ in q6v5_wcss_powerdown()
307 reset_control_assert(wcss->wcss_aon_reset); in q6v5_wcss_powerdown()
309 /* 7 - Disable WCSSAON_CONFIG 13 */ in q6v5_wcss_powerdown()
310 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
312 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
314 /* 8 - De-assert WCSS/Q6 HALTREQ */ in q6v5_wcss_powerdown()
315 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_powerdown()
320 static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) in q6v5_q6_powerdown() argument
326 /* 1 - Halt Q6 bus interface */ in q6v5_q6_powerdown()
327 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); in q6v5_q6_powerdown()
329 /* 2 - Disable Q6 Core clock */ in q6v5_q6_powerdown()
330 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
332 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
334 /* 3 - Clamp I/O */ in q6v5_q6_powerdown()
335 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
337 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
339 /* 4 - Clamp WL */ in q6v5_q6_powerdown()
341 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
343 /* 5 - Clear Erase standby */ in q6v5_q6_powerdown()
345 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
347 /* 6 - Clear Sleep RTN */ in q6v5_q6_powerdown()
349 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
351 /* 7 - turn off Q6 memory foot/head switch one bank at a time */ in q6v5_q6_powerdown()
353 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
355 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
359 /* 8 - Assert QMC memory RTN */ in q6v5_q6_powerdown()
360 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
362 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
364 /* 9 - Turn off BHS */ in q6v5_q6_powerdown()
366 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
369 /* 10 - Wait till BHS Reset is done */ in q6v5_q6_powerdown()
370 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, in q6v5_q6_powerdown()
374 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); in q6v5_q6_powerdown()
378 /* 11 - Assert WCSS reset */ in q6v5_q6_powerdown()
379 reset_control_assert(wcss->wcss_reset); in q6v5_q6_powerdown()
381 /* 12 - Assert Q6 reset */ in q6v5_q6_powerdown()
382 reset_control_assert(wcss->wcss_q6_reset); in q6v5_q6_powerdown()
389 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_stop() local
392 /* WCSS powerdown */ in q6v5_wcss_stop()
393 ret = qcom_q6v5_request_stop(&wcss->q6v5); in q6v5_wcss_stop()
394 if (ret == -ETIMEDOUT) { in q6v5_wcss_stop()
395 dev_err(wcss->dev, "timed out on wait\n"); in q6v5_wcss_stop()
399 ret = q6v5_wcss_powerdown(wcss); in q6v5_wcss_stop()
404 ret = q6v5_q6_powerdown(wcss); in q6v5_wcss_stop()
408 qcom_q6v5_unprepare(&wcss->q6v5); in q6v5_wcss_stop()
415 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_da_to_va() local
418 offset = da - wcss->mem_reloc; in q6v5_wcss_da_to_va()
419 if (offset < 0 || offset + len > wcss->mem_size) in q6v5_wcss_da_to_va()
422 return wcss->mem_region + offset; in q6v5_wcss_da_to_va()
427 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_load() local
430 ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, in q6v5_wcss_load()
431 0, wcss->mem_region, wcss->mem_phys, in q6v5_wcss_load()
432 wcss->mem_size, &wcss->mem_reloc); in q6v5_wcss_load()
436 qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); in q6v5_wcss_load()
449 static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) in q6v5_wcss_init_reset() argument
451 struct device *dev = wcss->dev; in q6v5_wcss_init_reset()
453 wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); in q6v5_wcss_init_reset()
454 if (IS_ERR(wcss->wcss_aon_reset)) { in q6v5_wcss_init_reset()
455 dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n"); in q6v5_wcss_init_reset()
456 return PTR_ERR(wcss->wcss_aon_reset); in q6v5_wcss_init_reset()
459 wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); in q6v5_wcss_init_reset()
460 if (IS_ERR(wcss->wcss_reset)) { in q6v5_wcss_init_reset()
461 dev_err(wcss->dev, "unable to acquire wcss_reset\n"); in q6v5_wcss_init_reset()
462 return PTR_ERR(wcss->wcss_reset); in q6v5_wcss_init_reset()
465 wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); in q6v5_wcss_init_reset()
466 if (IS_ERR(wcss->wcss_q6_reset)) { in q6v5_wcss_init_reset()
467 dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); in q6v5_wcss_init_reset()
468 return PTR_ERR(wcss->wcss_q6_reset); in q6v5_wcss_init_reset()
474 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, in q6v5_wcss_init_mmio() argument
482 wcss->reg_base = devm_ioremap_resource(&pdev->dev, res); in q6v5_wcss_init_mmio()
483 if (IS_ERR(wcss->reg_base)) in q6v5_wcss_init_mmio()
484 return PTR_ERR(wcss->reg_base); in q6v5_wcss_init_mmio()
487 wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); in q6v5_wcss_init_mmio()
488 if (IS_ERR(wcss->rmb_base)) in q6v5_wcss_init_mmio()
489 return PTR_ERR(wcss->rmb_base); in q6v5_wcss_init_mmio()
491 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, in q6v5_wcss_init_mmio()
492 "qcom,halt-regs", 3, 0, &args); in q6v5_wcss_init_mmio()
494 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); in q6v5_wcss_init_mmio()
495 return -EINVAL; in q6v5_wcss_init_mmio()
498 wcss->halt_map = syscon_node_to_regmap(args.np); in q6v5_wcss_init_mmio()
500 if (IS_ERR(wcss->halt_map)) in q6v5_wcss_init_mmio()
501 return PTR_ERR(wcss->halt_map); in q6v5_wcss_init_mmio()
503 wcss->halt_q6 = args.args[0]; in q6v5_wcss_init_mmio()
504 wcss->halt_wcss = args.args[1]; in q6v5_wcss_init_mmio()
505 wcss->halt_nc = args.args[2]; in q6v5_wcss_init_mmio()
510 static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) in q6v5_alloc_memory_region() argument
514 struct device *dev = wcss->dev; in q6v5_alloc_memory_region()
516 node = of_parse_phandle(dev->of_node, "memory-region", 0); in q6v5_alloc_memory_region()
522 dev_err(dev, "unable to acquire memory-region\n"); in q6v5_alloc_memory_region()
523 return -EINVAL; in q6v5_alloc_memory_region()
526 wcss->mem_phys = rmem->base; in q6v5_alloc_memory_region()
527 wcss->mem_reloc = rmem->base; in q6v5_alloc_memory_region()
528 wcss->mem_size = rmem->size; in q6v5_alloc_memory_region()
529 wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); in q6v5_alloc_memory_region()
530 if (!wcss->mem_region) { in q6v5_alloc_memory_region()
532 &rmem->base, &rmem->size); in q6v5_alloc_memory_region()
533 return -EBUSY; in q6v5_alloc_memory_region()
541 struct q6v5_wcss *wcss; in q6v5_wcss_probe() local
545 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops, in q6v5_wcss_probe()
546 "IPQ8074/q6_fw.mdt", sizeof(*wcss)); in q6v5_wcss_probe()
548 dev_err(&pdev->dev, "failed to allocate rproc\n"); in q6v5_wcss_probe()
549 return -ENOMEM; in q6v5_wcss_probe()
552 wcss = rproc->priv; in q6v5_wcss_probe()
553 wcss->dev = &pdev->dev; in q6v5_wcss_probe()
555 ret = q6v5_wcss_init_mmio(wcss, pdev); in q6v5_wcss_probe()
559 ret = q6v5_alloc_memory_region(wcss); in q6v5_wcss_probe()
563 ret = q6v5_wcss_init_reset(wcss); in q6v5_wcss_probe()
567 ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL); in q6v5_wcss_probe()
571 qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); in q6v5_wcss_probe()
572 qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); in q6v5_wcss_probe()
599 { .compatible = "qcom,ipq8074-wcss-pil" },
608 .name = "qcom-q6v5-wcss-pil",
614 MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");