67 #define QDSP6SS_PWR_CTL_REG		0x030  macro
669 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
671 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
672 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
677 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
680 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
682 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
686 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
710 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
712 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
720 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
722 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
723 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
729 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
732 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
734 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
736 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
738 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
742 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
1036 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()
1039 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()