169 		{ "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,  in rtmv20_properties_init()
171 		{ "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,  in rtmv20_properties_init()
173 		{ "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,  in rtmv20_properties_init()
175 		{ "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3,  in rtmv20_properties_init()
177 		{ "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,  in rtmv20_properties_init()
179 		{ "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3,  in rtmv20_properties_init()
181 		{ "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,  in rtmv20_properties_init()
183 		{ "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000,  in rtmv20_properties_init()
185 		{ "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,  in rtmv20_properties_init()
187 		{ "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },  in rtmv20_properties_init()
188 		{ "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,  in rtmv20_properties_init()
190 		{ "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,  in rtmv20_properties_init()
192 		{ "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },  in rtmv20_properties_init()
193 		{ "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },  in rtmv20_properties_init()
194 		{ "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },  in rtmv20_properties_init()
380 	{ .compatible = "richtek,rtmv20", },
395 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
396 MODULE_DESCRIPTION("Richtek RTMV20 Regulator Driver");