Lines Matching +full:0 +full:x5400
24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
37 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
38 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
48 SPMI_VS_SOFT_START_STR_0P05_UA = 0,
104 SPMI_REGULATOR_TYPE_BUCK = 0x03,
105 SPMI_REGULATOR_TYPE_LDO = 0x04,
106 SPMI_REGULATOR_TYPE_VS = 0x05,
107 SPMI_REGULATOR_TYPE_BOOST = 0x1b,
108 SPMI_REGULATOR_TYPE_FTS = 0x1c,
109 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
110 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
111 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
115 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
116 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
117 SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
118 SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
119 SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
120 SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
121 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
122 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
123 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
124 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
125 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
126 SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
127 SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
128 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
129 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
130 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
131 SPMI_REGULATOR_SUBTYPE_LN = 0x10,
132 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
133 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
134 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
135 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
136 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
137 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
138 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30,
139 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31,
140 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32,
141 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b,
142 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c,
143 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42,
144 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43,
145 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46,
146 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47,
147 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49,
148 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d,
149 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f,
150 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
151 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
152 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
153 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
154 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
155 SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
156 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
157 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
158 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
159 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a,
160 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
161 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
162 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
163 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
164 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
165 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
169 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
170 SPMI_COMMON_REG_TYPE = 0x04,
171 SPMI_COMMON_REG_SUBTYPE = 0x05,
172 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
173 SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
174 SPMI_COMMON_REG_MODE = 0x45,
175 SPMI_COMMON_REG_ENABLE = 0x46,
176 SPMI_COMMON_REG_PULL_DOWN = 0x48,
177 SPMI_COMMON_REG_SOFT_START = 0x4c,
178 SPMI_COMMON_REG_STEP_CTRL = 0x61,
187 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40,
188 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41,
189 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68,
190 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69,
194 SPMI_VS_REG_OCP = 0x4a,
195 SPMI_VS_REG_SOFT_START = 0x4c,
199 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
203 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
207 SAW3_SECURE = 0x00,
208 SAW3_ID = 0x04,
209 SAW3_SPM_STS = 0x0C,
210 SAW3_AVS_STS = 0x10,
211 SAW3_PMIC_STS = 0x14,
212 SAW3_RST = 0x18,
213 SAW3_VCTL = 0x1C,
214 SAW3_AVS_CTL = 0x20,
215 SAW3_AVS_LIMIT = 0x24,
216 SAW3_AVS_DLY = 0x28,
217 SAW3_AVS_HYSTERESIS = 0x2C,
218 SAW3_SPM_STS2 = 0x38,
219 SAW3_SPM_PMIC_DATA_3 = 0x4C,
220 SAW3_VERSION = 0xFD0,
223 /* Used for indexing into ctrl_reg. These are offets from 0x40 */
225 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
232 #define SPMI_COMMON_ENABLE_MASK 0x80
233 #define SPMI_COMMON_ENABLE 0x80
234 #define SPMI_COMMON_DISABLE 0x00
235 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
236 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
237 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
238 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
239 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
242 #define SPMI_COMMON_MODE_HPM_MASK 0x80
243 #define SPMI_COMMON_MODE_AUTO_MASK 0x40
244 #define SPMI_COMMON_MODE_BYPASS_MASK 0x20
245 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
246 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
247 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
248 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
249 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
250 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
258 #define SPMI_FTSMPS426_MODE_MASK 0x07
261 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
264 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
267 #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
270 #define SPMI_VS_OCP_OVERRIDE 0x01
271 #define SPMI_VS_OCP_NO_OVERRIDE 0x00
274 #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
275 #define SPMI_VS_SOFT_START_SEL_MASK 0x03
278 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
279 #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
286 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
288 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
289 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
305 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03
306 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0
325 #define ULT_SMPS_RANGE_SPLIT 0x60
330 * set point register value 0x00
343 * (max_uV - min_uV) % step_uV == 0
344 * (set_point_min_uV - min_uV) % step_uV == 0*
345 * (set_point_max_uV - min_uV) % step_uV == 0*
348 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
466 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
472 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
473 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
474 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
479 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
483 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
488 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
489 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
493 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
498 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
502 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
506 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
510 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
511 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
515 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
519 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
523 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
527 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
531 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
535 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
539 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000),
543 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
590 vreg->ocp_count = 0; in spmi_regulator_vs_enable()
614 lim_min_uV = vreg->set_points->range[0].set_point_min_uV; in spmi_regulator_select_voltage()
629 for (i = vreg->set_points->count - 1; i > 0; i--) { in spmi_regulator_select_voltage()
631 if (uV > range_max_uV && range_max_uV > 0) in spmi_regulator_select_voltage()
653 selector = 0; in spmi_regulator_select_voltage()
654 for (i = 0; i < range_id; i++) in spmi_regulator_select_voltage()
681 return 0; in spmi_sw_selector_to_hw()
693 unsigned sw_sel = 0; in spmi_hw_selector_to_sw()
776 selector = 0; in spmi_regulator_select_voltage_same_range()
777 for (i = 0; i < vreg->set_points->count; i++) { in spmi_regulator_select_voltage_same_range()
822 buf[0] = range_sel; in spmi_regulator_common_set_voltage()
839 buf[0] = mV & 0xff; in spmi_regulator_ftsmps426_set_voltage()
880 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; in spmi_regulator_ftsmps426_get_voltage()
933 * In case of range 0: voltage_sel is a 7 bit value, can be written in spmi_regulator_ult_lo_smps_set_voltage()
942 voltage_sel, 0xff); in spmi_regulator_ult_lo_smps_set_voltage()
967 int uV = 0; in spmi_regulator_common_list_voltage()
971 return 0; in spmi_regulator_common_list_voltage()
973 for (i = 0; i < vreg->set_points->count; i++) { in spmi_regulator_common_list_voltage()
991 u8 val = 0; in spmi_regulator_common_set_bypass()
1063 val = 0; in spmi_regulator_common_set_mode()
1141 if (ilim_uA > max || ilim_uA <= 0) in spmi_regulator_set_ilim()
1190 vreg->ocp_count = 0; in spmi_regulator_vs_ocp_isr()
1192 /* Wait for switch output to settle back to 0 V after OCP triggered. */ in spmi_regulator_vs_ocp_isr()
1213 #define SAW3_VCTL_DATA_MASK 0xFF
1214 #define SAW3_VCTL_CLEAR_MASK 0x700FF
1215 #define SAW3_AVS_CTL_EN_MASK 0x1
1216 #define SAW3_AVS_CTL_TGGL_MASK 0x8000000
1217 #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00
1263 pmic_sts &= 0x3f; in spmi_saw_set_vdd()
1283 if (0 != range_sel) { in spmi_regulator_saw_set_voltage()
1290 return smp_call_function_single(0, spmi_saw_set_vdd, \ in spmi_regulator_saw_set_voltage()
1452 #define INF 0xFF
1456 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
1457 SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
1458 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
1459 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
1460 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
1463 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
1464 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
1467 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
1468 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
1469 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
1470 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
1471 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
1472 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
1473 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
1474 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
1475 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
1476 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
1477 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
1478 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1480 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1482 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426,
1484 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426,
1486 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426,
1488 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1490 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1492 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426,
1494 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426,
1496 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426,
1498 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426,
1500 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426,
1502 SPMI_VREG_VS(LV100, 0, INF),
1503 SPMI_VREG_VS(LV300, 0, INF),
1504 SPMI_VREG_VS(MV300, 0, INF),
1505 SPMI_VREG_VS(MV500, 0, INF),
1506 SPMI_VREG_VS(HDMI, 0, INF),
1507 SPMI_VREG_VS(OTG, 0, INF),
1508 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
1509 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1510 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
1511 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
1512 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1513 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1515 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1517 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1519 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1521 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1522 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1523 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1524 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1525 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1526 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1527 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1528 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1529 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1530 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1539 n = 0; in spmi_calculate_num_voltages()
1576 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { in spmi_regulator_match()
1585 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", in spmi_regulator_match()
1602 return 0; in spmi_regulator_match()
1608 u8 reg = 0; in spmi_regulator_init_slew_rate()
1643 /* Ensure that the slew rate is greater than 0 */ in spmi_regulator_init_slew_rate()
1653 u8 reg = 0; in spmi_regulator_init_slew_rate_ftsmps426()
1655 const struct spmi_voltage_range *range = &vreg->set_points->range[0]; in spmi_regulator_init_slew_rate_ftsmps426()
1672 /* Ensure that the slew rate is greater than 0 */ in spmi_regulator_init_slew_rate_ftsmps426()
1749 return 0; in spmi_regulator_init_registers()
1833 vreg->ocp_irq = 0; in spmi_regulator_of_parse()
1839 if (ret < 0) { in spmi_regulator_of_parse()
1848 return 0; in spmi_regulator_of_parse()
1852 { "s1", 0x1400, "vdd_s1", },
1853 { "s2", 0x1700, "vdd_s2", },
1854 { "s3", 0x1a00, "vdd_s3", },
1855 { "s4", 0xa000, },
1856 { "l1", 0x4000, "vdd_l1_l3", },
1857 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
1858 { "l3", 0x4200, "vdd_l1_l3", },
1859 { "l4", 0x4300, "vdd_l4_l11", },
1860 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
1861 { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
1862 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
1863 { "l8", 0x4700, "vdd_l8_l16_l18_19", },
1864 { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
1865 { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
1866 { "l11", 0x4a00, "vdd_l4_l11", },
1867 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
1868 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
1869 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
1870 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
1871 { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
1872 { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
1873 { "l18", 0x5100, "vdd_l8_l16_l18_19", },
1874 { "l19", 0x5200, "vdd_l8_l16_l18_19", },
1875 { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
1876 { "l21", 0x5400, "vdd_l21", },
1877 { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
1878 { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
1879 { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
1880 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
1881 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
1882 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
1883 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
1884 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
1889 { "s1", 0x1400, "vdd_s1", },
1890 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
1891 { "s3", 0x1a00, "vdd_s3", },
1892 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
1893 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
1894 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
1895 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
1896 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
1901 { "s1", 0x1400, "vdd_s1", },
1902 { "s2", 0x1700, "vdd_s2", },
1903 { "s3", 0x1a00, "vdd_s3", },
1904 { "s4", 0x1d00, "vdd_s4", },
1905 { "l1", 0x4000, "vdd_l1_l3", },
1906 { "l2", 0x4100, "vdd_l2", },
1907 { "l3", 0x4200, "vdd_l1_l3", },
1908 { "l4", 0x4300, "vdd_l4_l5_l6", },
1909 { "l5", 0x4400, "vdd_l4_l5_l6", },
1910 { "l6", 0x4500, "vdd_l4_l5_l6", },
1911 { "l7", 0x4600, "vdd_l7", },
1912 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
1913 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
1914 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
1915 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
1916 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
1917 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
1918 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
1919 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
1920 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
1921 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
1922 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
1927 { "s1", 0x1400, "vdd_s1", },
1928 { "s2", 0x1700, "vdd_s2", },
1929 { "s3", 0x1a00, "vdd_s3", },
1930 { "s4", 0x1d00, "vdd_s4", },
1931 { "s5", 0x2000, "vdd_s5", },
1932 { "s6", 0x2300, "vdd_s6", },
1933 { "l1", 0x4000, "vdd_l1_l19", },
1934 { "l2", 0x4100, "vdd_l2_l23", },
1935 { "l3", 0x4200, "vdd_l3", },
1936 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
1937 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
1938 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
1939 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
1940 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
1941 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
1942 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
1943 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
1944 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
1945 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
1946 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
1947 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
1948 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
1949 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
1950 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
1951 { "l19", 0x5200, "vdd_l1_l19", },
1952 { "l20", 0x5300, "vdd_l20", },
1953 { "l21", 0x5400, "vdd_l21", },
1954 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
1955 { "l23", 0x5600, "vdd_l2_l23", },
1960 { "s1", 0x1400, "vdd_s1", },
1961 { "s2", 0x1700, "vdd_s2", },
1962 { "s3", 0x1a00, "vdd_s3", },
1963 { "s4", 0x1d00, "vdd_s4", },
1964 { "s5", 0x2000, "vdd_s5", },
1965 { "s6", 0x2300, "vdd_s6", },
1966 { "s7", 0x2600, "vdd_s7", },
1967 { "s8", 0x2900, "vdd_s8", },
1968 { "s9", 0x2c00, "vdd_s9", },
1969 { "s10", 0x2f00, "vdd_s10", },
1970 { "s11", 0x3200, "vdd_s11", },
1971 { "s12", 0x3500, "vdd_s12", },
1972 { "l1", 0x4000, "vdd_l1", },
1973 { "l2", 0x4100, "vdd_l2_l26_l28", },
1974 { "l3", 0x4200, "vdd_l3_l11", },
1975 { "l4", 0x4300, "vdd_l4_l27_l31", },
1976 { "l5", 0x4400, "vdd_l5_l7", },
1977 { "l6", 0x4500, "vdd_l6_l12_l32", },
1978 { "l7", 0x4600, "vdd_l5_l7", },
1979 { "l8", 0x4700, "vdd_l8_l16_l30", },
1980 { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
1981 { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
1982 { "l11", 0x4a00, "vdd_l3_l11", },
1983 { "l12", 0x4b00, "vdd_l6_l12_l32", },
1984 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
1985 { "l14", 0x4d00, "vdd_l14_l15", },
1986 { "l15", 0x4e00, "vdd_l14_l15", },
1987 { "l16", 0x4f00, "vdd_l8_l16_l30", },
1988 { "l17", 0x5000, "vdd_l17_l29", },
1989 { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
1990 { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
1991 { "l20", 0x5300, "vdd_l20_l21", },
1992 { "l21", 0x5400, "vdd_l20_l21", },
1993 { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
1994 { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
1995 { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
1996 { "l25", 0x5800, "vdd_l25", },
1997 { "l26", 0x5900, "vdd_l2_l26_l28", },
1998 { "l27", 0x5a00, "vdd_l4_l27_l31", },
1999 { "l28", 0x5b00, "vdd_l2_l26_l28", },
2000 { "l29", 0x5c00, "vdd_l17_l29", },
2001 { "l30", 0x5d00, "vdd_l8_l16_l30", },
2002 { "l31", 0x5e00, "vdd_l4_l27_l31", },
2003 { "l32", 0x5f00, "vdd_l6_l12_l32", },
2004 { "lvs1", 0x8000, "vdd_lvs_1_2", },
2005 { "lvs2", 0x8100, "vdd_lvs_1_2", },
2010 { "s1", 0x1400, "vdd_s1", },
2011 { "s2", 0x1700, "vdd_s2", },
2012 { "s3", 0x1a00, "vdd_s3", },
2013 { "l1", 0x4000, "vdd_l1", },
2018 { "s1", 0x1400, "vdd_s1", },
2019 { "s2", 0x1700, "vdd_s2", },
2020 { "s3", 0x1a00, "vdd_s3", },
2021 { "s4", 0x1d00, "vdd_s3", },
2022 { "s5", 0x2000, "vdd_s5", },
2023 { "s6", 0x2300, "vdd_s6", },
2024 { "l1", 0x4000, "vdd_l1_l6_l7", },
2025 { "l2", 0x4100, "vdd_l2_l3", },
2026 { "l3", 0x4200, "vdd_l2_l3", },
2028 { "l5", 0x4400, "vdd_l5", },
2029 { "l6", 0x4500, "vdd_l1_l6_l7", },
2030 { "l7", 0x4600, "vdd_l1_l6_l7", },
2031 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2032 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2033 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2034 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2035 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2036 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2037 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2038 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
2039 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
2040 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
2041 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
2042 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
2047 { "s1", 0x1400, "vdd_s1", },
2048 { "s2", 0x1700, "vdd_s2", },
2049 { "s3", 0x1a00, "vdd_s3", },
2050 { "s4", 0x1d00, "vdd_s4", },
2051 { "s5", 0x2000, "vdd_s5", },
2052 { "l1", 0x4000, "vdd_l1_l9_l10", },
2053 { "l2", 0x4100, "vdd_l2", },
2054 { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
2055 { "l4", 0x4300, "vdd_l4_l6", },
2056 { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
2057 { "l6", 0x4500, "vdd_l4_l6", },
2058 { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
2059 { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
2060 { "l9", 0x4800, "vdd_l1_l9_l10", },
2061 { "l10", 0x4900, "vdd_l1_l9_l10", },
2067 { "s2", 0x1700, "vdd_s2", },
2068 { "s5", 0x2000, "vdd_s5", },
2073 { "s1", 0x1400, "vdd_s1", },
2074 { "s2", 0x1700, "vdd_s2", },
2075 { "s3", 0x1a00, "vdd_s3", },
2076 { "s4", 0x1d00, "vdd_s4", },
2081 { "s3", 0x1a00, "vdd_s3"},
2133 syscon = of_parse_phandle(node, "qcom,saw-reg", 0); in qcom_spmi_regulator_probe()
2160 if (vreg->ocp_irq < 0) { in qcom_spmi_regulator_probe()
2214 return 0; in qcom_spmi_regulator_probe()
2232 return 0; in qcom_spmi_regulator_remove()