Lines Matching +full:0 +full:xe0
55 .enable_mask = BIT(0), \
105 REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
109 REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
113 REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
186 if (ret != 0) { in mt6397_regulator_set_mode()
192 return 0; in mt6397_regulator_set_mode()
201 if (ret != 0) { in mt6397_regulator_get_mode()
224 if (ret != 0) { in mt6397_get_status()
269 buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
272 buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
276 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5,
280 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5,
283 buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
286 MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
289 MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
292 buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
297 MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
301 MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
303 MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
305 MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
307 MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
309 MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
311 MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
313 MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
315 MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
317 MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
319 MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
328 for (i = 0; i < MT6397_MAX_REGULATOR; i++) { in mt6397_set_buck_vosel_reg()
332 ®val) < 0) { in mt6397_set_buck_vosel_reg()
345 return 0; in mt6397_set_buck_vosel_reg()
361 if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { in mt6397_regulator_probe()
365 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); in mt6397_regulator_probe()
367 version = (reg_value & 0xFF); in mt6397_regulator_probe()
377 for (i = 0; i < MT6397_MAX_REGULATOR; i++) { in mt6397_regulator_probe()
390 return 0; in mt6397_regulator_probe()
394 {"mt6397-regulator", 0},