Lines Matching +full:0 +full:xf00
16 #define MT6358_BUCK_MODE_AUTO 0
57 .enable_mask = BIT(0), \
61 .qi = BIT(0), \
112 .enable_mask = BIT(0), \
118 .qi = BIT(0), \
141 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
145 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
149 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
153 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
204 0, 12,
212 0, 1, 2, 4, 5, 9, 11, 13,
232 0, 7, 9, 10, 11, 12,
278 if (ret != 0) { in mt6358_get_voltage_sel()
287 for (idx = 0; idx < info->desc.n_voltages; idx++) { in mt6358_get_voltage_sel()
301 if (ret != 0) { in mt6358_get_buck_voltage_sel()
320 if (ret != 0) { in mt6358_get_status()
361 if (ret != 0) { in mt6358_regulator_get_mode()
414 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
415 0, MT6358_VDRAM1_ANA_CON0, 8),
417 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
418 0, MT6358_VCORE_VGPU_ANA_CON0, 1),
420 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0,
423 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
424 0, MT6358_VPROC_ANA_CON0, 1),
426 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
427 0, MT6358_VPROC_ANA_CON0, 2),
429 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, 0,
432 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0,
435 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
436 0, MT6358_VMODEM_ANA_CON0, 8),
438 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0,
441 MT6358_LDO_VRF12_CON0, 0, 1200000),
443 MT6358_LDO_VIO18_CON0, 0, 1800000),
445 MT6358_LDO_VCAMIO_CON0, 0, 1800000),
446 MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
447 MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
448 MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
449 MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
451 MT6358_LDO_VAUX18_CON0, 0, 1800000),
453 MT6358_LDO_VBIF28_CON0, 0, 2800000),
454 MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
455 MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
456 MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
458 MT6358_LDO_VAUD28_CON0, 0, 2800000),
460 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10, 0),
462 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8),
464 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8),
466 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8),
468 MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8),
470 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8),
472 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8),
474 MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8),
476 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8),
479 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
482 0, MT6358_VCN33_ANA_CON0, 0x300, 8),
484 MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8),
486 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8),
488 MT6358_LDO_VLDO28_CON0_0, 0,
489 MT6358_VLDO28_ANA_CON0, 0x300, 8),
491 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8),
493 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8,
494 MT6358_LDO_VSRAM_CON0, 0x7f),
496 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8,
497 MT6358_LDO_VSRAM_CON2, 0x7f),
499 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8,
500 MT6358_LDO_VSRAM_CON3, 0x7f),
502 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8,
503 MT6358_LDO_VSRAM_CON1, 0x7f),
513 for (i = 0; i < MT6358_MAX_REGULATOR; i++) { in mt6358_regulator_probe()
528 return 0; in mt6358_regulator_probe()
532 {"mt6358-regulator", 0},