192 	if (ret < 0) {  in ab8500_regulator_enable()
199 		"%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_enable()
218 		info->update_mask, 0x0);  in ab8500_regulator_disable()
219 	if (ret < 0) {  in ab8500_regulator_disable()
226 		"%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_disable()
228 		info->update_mask, 0x0);  in ab8500_regulator_disable()
246 	if (ret < 0) {  in ab8500_regulator_is_enabled()
248 			"couldn't read 0x%x register\n", info->update_reg);  in ab8500_regulator_is_enabled()
253 		"%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"  in ab8500_regulator_is_enabled()
254 		" 0x%x\n",  in ab8500_regulator_is_enabled()
261 		return 0;  in ab8500_regulator_is_enabled()
288 	int ret = 0;  in ab8500_regulator_set_mode()
348 		if (ret < 0) {  in ab8500_regulator_set_mode()
356 			"0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_set_mode()
435 	if (ret < 0) {  in ab8500_regulator_get_voltage_sel()
443 		"0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_get_voltage_sel()
470 	if (ret < 0)  in ab8500_regulator_set_voltage_sel()
475 		"%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"  in ab8500_regulator_set_voltage_sel()
476 		" 0x%x\n",  in ab8500_regulator_set_voltage_sel()
552 		.update_bank		= 0x04,
553 		.update_reg		= 0x09,
554 		.update_mask		= 0x03,
555 		.update_val		= 0x01,
556 		.update_val_idle	= 0x03,
557 		.update_val_normal	= 0x01,
558 		.voltage_bank		= 0x04,
559 		.voltage_reg		= 0x1f,
560 		.voltage_mask		= 0x0f,
575 		.update_bank		= 0x04,
576 		.update_reg		= 0x09,
577 		.update_mask		= 0x0c,
578 		.update_val		= 0x04,
579 		.update_val_idle	= 0x0c,
580 		.update_val_normal	= 0x04,
581 		.voltage_bank		= 0x04,
582 		.voltage_reg		= 0x20,
583 		.voltage_mask		= 0x0f,
598 		.update_bank		= 0x04,
599 		.update_reg		= 0x0a,
600 		.update_mask		= 0x03,
601 		.update_val		= 0x01,
602 		.update_val_idle	= 0x03,
603 		.update_val_normal	= 0x01,
604 		.voltage_bank		= 0x04,
605 		.voltage_reg		= 0x21,
606 		.voltage_mask		= 0x07,
620 		.update_bank		= 0x03,
621 		.update_reg		= 0x80,
622 		.update_mask		= 0x44,
623 		.update_val		= 0x44,
624 		.update_val_idle	= 0x44,
625 		.update_val_normal	= 0x04,
626 		.voltage_bank		= 0x03,
627 		.voltage_reg		= 0x80,
628 		.voltage_mask		= 0x38,
648 		.update_bank		= 0x03,
649 		.update_reg		= 0x80,
650 		.update_mask		= 0x82,
651 		.update_val		= 0x02,
652 		.update_val_idle	= 0x82,
653 		.update_val_normal	= 0x02,
666 		.update_bank		= 0x03,
667 		.update_reg		= 0x83,
668 		.update_mask		= 0x02,
669 		.update_val		= 0x02,
682 		.update_bank		= 0x03,
683 		.update_reg		= 0x83,
684 		.update_mask		= 0x08,
685 		.update_val		= 0x08,
698 		.update_bank		= 0x03,
699 		.update_reg		= 0x83,
700 		.update_mask		= 0x10,
701 		.update_val		= 0x10,
714 		.update_bank		= 0x03,
715 		.update_reg		= 0x83,
716 		.update_mask		= 0x04,
717 		.update_val		= 0x04,
735 		.update_bank		= 0x04,
736 		.update_reg		= 0x06,
737 		.update_mask		= 0x0c,
738 		.update_val		= 0x04,
739 		.update_val_idle	= 0x0c,
740 		.update_val_normal	= 0x04,
764 		.update_bank		= 0x04,
765 		.update_reg		= 0x09,
766 		.update_mask		= 0x03,
767 		.update_val		= 0x01,
768 		.update_val_idle	= 0x03,
769 		.update_val_normal	= 0x01,
770 		.voltage_bank		= 0x04,
771 		.voltage_reg		= 0x1f,
772 		.voltage_mask		= 0x0f,
785 		.update_bank		= 0x04,
786 		.update_reg		= 0x09,
787 		.update_mask		= 0x0c,
788 		.update_val		= 0x04,
789 		.update_val_idle	= 0x0c,
790 		.update_val_normal	= 0x04,
791 		.voltage_bank		= 0x04,
792 		.voltage_reg		= 0x20,
793 		.voltage_mask		= 0x0f,
806 		.update_bank		= 0x04,
807 		.update_reg		= 0x0a,
808 		.update_mask		= 0x03,
809 		.update_val		= 0x01,
810 		.update_val_idle	= 0x03,
811 		.update_val_normal	= 0x01,
812 		.voltage_bank		= 0x04,
813 		.voltage_reg		= 0x21,
814 		.voltage_mask		= 0x07,
828 		.update_bank		= 0x04,
829 		.update_reg		= 0x2e,
830 		.update_mask		= 0x03,
831 		.update_val		= 0x01,
832 		.update_val_idle	= 0x03,
833 		.update_val_normal	= 0x01,
835 		.voltage_bank		= 0x04,
836 		.voltage_reg		= 0x2f,
837 		.voltage_mask		= 0x0f,
851 		.update_bank		= 0x01,
852 		.update_reg		= 0x55,
853 		.update_mask		= 0x18,
854 		.update_val		= 0x10,
855 		.update_val_idle	= 0x18,
856 		.update_val_normal	= 0x10,
857 		.voltage_bank		= 0x01,
858 		.voltage_reg		= 0x55,
859 		.voltage_mask		= 0x07,
873 		.update_bank		= 0x01,
874 		.update_reg		= 0x56,
875 		.update_mask		= 0x18,
876 		.update_val		= 0x10,
877 		.update_val_idle	= 0x18,
878 		.update_val_normal	= 0x10,
879 		.voltage_bank		= 0x01,
880 		.voltage_reg		= 0x56,
881 		.voltage_mask		= 0x07,
894 		.update_bank		= 0x03,
895 		.update_reg		= 0x80,
896 		.update_mask		= 0x44,
897 		.update_val		= 0x04,
898 		.update_val_idle	= 0x44,
899 		.update_val_normal	= 0x04,
900 		.voltage_bank		= 0x03,
901 		.voltage_reg		= 0x80,
902 		.voltage_mask		= 0x38,
922 		.update_bank		= 0x03,
923 		.update_reg		= 0x80,
924 		.update_mask		= 0x82,
925 		.update_val		= 0x02,
926 		.update_val_idle	= 0x82,
927 		.update_val_normal	= 0x02,
939 		.update_bank		= 0x03,
940 		.update_reg		= 0x83,
941 		.update_mask		= 0x02,
942 		.update_val		= 0x02,
943 		.voltage_bank		= 0x01,
944 		.voltage_reg		= 0x57,
945 		.voltage_mask		= 0x70,
958 		.update_bank		= 0x03,
959 		.update_reg		= 0x83,
960 		.update_mask		= 0x08,
961 		.update_val		= 0x08,
962 		.mode_bank		= 0x01,
963 		.mode_reg		= 0x54,
964 		.mode_mask		= 0x04,
965 		.mode_val_idle		= 0x04,
966 		.mode_val_normal	= 0x00,
979 		.update_bank		= 0x03,
980 		.update_reg		= 0x83,
981 		.update_mask		= 0x10,
982 		.update_val		= 0x10,
983 		.mode_bank		= 0x01,
984 		.mode_reg		= 0x54,
985 		.mode_mask		= 0x04,
986 		.mode_val_idle		= 0x04,
987 		.mode_val_normal	= 0x00,
999 		.update_bank		= 0x03,
1000 		.update_reg		= 0x83,
1001 		.update_mask		= 0x04,
1002 		.update_val		= 0x04,
1018 		.update_bank		= 0x04,
1019 		.update_reg		= 0x06,
1020 		.update_mask		= 0x0c,
1021 		.update_val		= 0x04,
1022 		.update_val_idle	= 0x0c,
1023 		.update_val_normal	= 0x04,
1024 		.voltage_bank		= 0x04,
1025 		.voltage_reg		= 0x29,
1026 		.voltage_mask		= 0x7,
1054 	 * 0x30, VanaRequestCtrl
1055 	 * 0xc0, VextSupply1RequestCtrl
1057 	REG_INIT(AB8500_REGUREQUESTCTRL2,	0x03, 0x04, 0xf0),
1059 	 * 0x03, VextSupply2RequestCtrl
1060 	 * 0x0c, VextSupply3RequestCtrl
1061 	 * 0x30, Vaux1RequestCtrl
1062 	 * 0xc0, Vaux2RequestCtrl
1064 	REG_INIT(AB8500_REGUREQUESTCTRL3,	0x03, 0x05, 0xff),
1066 	 * 0x03, Vaux3RequestCtrl
1067 	 * 0x04, SwHPReq
1069 	REG_INIT(AB8500_REGUREQUESTCTRL4,	0x03, 0x06, 0x07),
1071 	 * 0x08, VanaSysClkReq1HPValid
1072 	 * 0x20, Vaux1SysClkReq1HPValid
1073 	 * 0x40, Vaux2SysClkReq1HPValid
1074 	 * 0x80, Vaux3SysClkReq1HPValid
1076 	REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1,	0x03, 0x07, 0xe8),
1078 	 * 0x10, VextSupply1SysClkReq1HPValid
1079 	 * 0x20, VextSupply2SysClkReq1HPValid
1080 	 * 0x40, VextSupply3SysClkReq1HPValid
1082 	REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2,	0x03, 0x08, 0x70),
1084 	 * 0x08, VanaHwHPReq1Valid
1085 	 * 0x20, Vaux1HwHPReq1Valid
1086 	 * 0x40, Vaux2HwHPReq1Valid
1087 	 * 0x80, Vaux3HwHPReq1Valid
1089 	REG_INIT(AB8500_REGUHWHPREQ1VALID1,	0x03, 0x09, 0xe8),
1091 	 * 0x01, VextSupply1HwHPReq1Valid
1092 	 * 0x02, VextSupply2HwHPReq1Valid
1093 	 * 0x04, VextSupply3HwHPReq1Valid
1095 	REG_INIT(AB8500_REGUHWHPREQ1VALID2,	0x03, 0x0a, 0x07),
1097 	 * 0x08, VanaHwHPReq2Valid
1098 	 * 0x20, Vaux1HwHPReq2Valid
1099 	 * 0x40, Vaux2HwHPReq2Valid
1100 	 * 0x80, Vaux3HwHPReq2Valid
1102 	REG_INIT(AB8500_REGUHWHPREQ2VALID1,	0x03, 0x0b, 0xe8),
1104 	 * 0x01, VextSupply1HwHPReq2Valid
1105 	 * 0x02, VextSupply2HwHPReq2Valid
1106 	 * 0x04, VextSupply3HwHPReq2Valid
1108 	REG_INIT(AB8500_REGUHWHPREQ2VALID2,	0x03, 0x0c, 0x07),
1110 	 * 0x20, VanaSwHPReqValid
1111 	 * 0x80, Vaux1SwHPReqValid
1113 	REG_INIT(AB8500_REGUSWHPREQVALID1,	0x03, 0x0d, 0xa0),
1115 	 * 0x01, Vaux2SwHPReqValid
1116 	 * 0x02, Vaux3SwHPReqValid
1117 	 * 0x04, VextSupply1SwHPReqValid
1118 	 * 0x08, VextSupply2SwHPReqValid
1119 	 * 0x10, VextSupply3SwHPReqValid
1121 	REG_INIT(AB8500_REGUSWHPREQVALID2,	0x03, 0x0e, 0x1f),
1123 	 * 0x02, SysClkReq2Valid1
1124 	 * 0x04, SysClkReq3Valid1
1125 	 * 0x08, SysClkReq4Valid1
1126 	 * 0x10, SysClkReq5Valid1
1127 	 * 0x20, SysClkReq6Valid1
1128 	 * 0x40, SysClkReq7Valid1
1129 	 * 0x80, SysClkReq8Valid1
1131 	REG_INIT(AB8500_REGUSYSCLKREQVALID1,	0x03, 0x0f, 0xfe),
1133 	 * 0x02, SysClkReq2Valid2
1134 	 * 0x04, SysClkReq3Valid2
1135 	 * 0x08, SysClkReq4Valid2
1136 	 * 0x10, SysClkReq5Valid2
1137 	 * 0x20, SysClkReq6Valid2
1138 	 * 0x40, SysClkReq7Valid2
1139 	 * 0x80, SysClkReq8Valid2
1141 	REG_INIT(AB8500_REGUSYSCLKREQVALID2,	0x03, 0x10, 0xfe),
1143 	 * 0x02, VTVoutEna
1144 	 * 0x04, Vintcore12Ena
1145 	 * 0x38, Vintcore12Sel
1146 	 * 0x40, Vintcore12LP
1147 	 * 0x80, VTVoutLP
1149 	REG_INIT(AB8500_REGUMISC1,		0x03, 0x80, 0xfe),
1151 	 * 0x02, VaudioEna
1152 	 * 0x04, VdmicEna
1153 	 * 0x08, Vamic1Ena
1154 	 * 0x10, Vamic2Ena
1156 	REG_INIT(AB8500_VAUDIOSUPPLY,		0x03, 0x83, 0x1e),
1158 	 * 0x01, Vamic1_dzout
1159 	 * 0x02, Vamic2_dzout
1161 	REG_INIT(AB8500_REGUCTRL1VAMIC,		0x03, 0x84, 0x03),
1163 	 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1164 	 * 0x0c, VanaRegu
1166 	REG_INIT(AB8500_VPLLVANAREGU,		0x04, 0x06, 0x0f),
1168 	 * 0x01, VrefDDREna
1169 	 * 0x02, VrefDDRSleepMode
1171 	REG_INIT(AB8500_VREFDDR,		0x04, 0x07, 0x03),
1173 	 * 0x03, VextSupply1Regu
1174 	 * 0x0c, VextSupply2Regu
1175 	 * 0x30, VextSupply3Regu
1176 	 * 0x40, ExtSupply2Bypass
1177 	 * 0x80, ExtSupply3Bypass
1179 	REG_INIT(AB8500_EXTSUPPLYREGU,		0x04, 0x08, 0xff),
1181 	 * 0x03, Vaux1Regu
1182 	 * 0x0c, Vaux2Regu
1184 	REG_INIT(AB8500_VAUX12REGU,		0x04, 0x09, 0x0f),
1186 	 * 0x03, Vaux3Regu
1188 	REG_INIT(AB8500_VRF1VAUX3REGU,		0x04, 0x0a, 0x03),
1190 	 * 0x0f, Vaux1Sel
1192 	REG_INIT(AB8500_VAUX1SEL,		0x04, 0x1f, 0x0f),
1194 	 * 0x0f, Vaux2Sel
1196 	REG_INIT(AB8500_VAUX2SEL,		0x04, 0x20, 0x0f),
1198 	 * 0x07, Vaux3Sel
1200 	REG_INIT(AB8500_VRF1VAUX3SEL,		0x04, 0x21, 0x07),
1202 	 * 0x01, VextSupply12LP
1204 	REG_INIT(AB8500_REGUCTRL2SPARE,		0x04, 0x22, 0x01),
1206 	 * 0x04, Vaux1Disch
1207 	 * 0x08, Vaux2Disch
1208 	 * 0x10, Vaux3Disch
1209 	 * 0x20, Vintcore12Disch
1210 	 * 0x40, VTVoutDisch
1211 	 * 0x80, VaudioDisch
1213 	REG_INIT(AB8500_REGUCTRLDISCH,		0x04, 0x43, 0xfc),
1215 	 * 0x02, VanaDisch
1216 	 * 0x04, VdmicPullDownEna
1217 	 * 0x10, VdmicDisch
1219 	REG_INIT(AB8500_REGUCTRLDISCH2,		0x04, 0x44, 0x16),
1225 	 * 0x03, VarmRequestCtrl
1226 	 * 0x0c, VsmpsCRequestCtrl
1227 	 * 0x30, VsmpsARequestCtrl
1228 	 * 0xc0, VsmpsBRequestCtrl
1230 	REG_INIT(AB8505_REGUREQUESTCTRL1,	0x03, 0x03, 0xff),
1232 	 * 0x03, VsafeRequestCtrl
1233 	 * 0x0c, VpllRequestCtrl
1234 	 * 0x30, VanaRequestCtrl
1236 	REG_INIT(AB8505_REGUREQUESTCTRL2,	0x03, 0x04, 0x3f),
1238 	 * 0x30, Vaux1RequestCtrl
1239 	 * 0xc0, Vaux2RequestCtrl
1241 	REG_INIT(AB8505_REGUREQUESTCTRL3,	0x03, 0x05, 0xf0),
1243 	 * 0x03, Vaux3RequestCtrl
1244 	 * 0x04, SwHPReq
1246 	REG_INIT(AB8505_REGUREQUESTCTRL4,	0x03, 0x06, 0x07),
1248 	 * 0x01, VsmpsASysClkReq1HPValid
1249 	 * 0x02, VsmpsBSysClkReq1HPValid
1250 	 * 0x04, VsafeSysClkReq1HPValid
1251 	 * 0x08, VanaSysClkReq1HPValid
1252 	 * 0x10, VpllSysClkReq1HPValid
1253 	 * 0x20, Vaux1SysClkReq1HPValid
1254 	 * 0x40, Vaux2SysClkReq1HPValid
1255 	 * 0x80, Vaux3SysClkReq1HPValid
1257 	REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1,	0x03, 0x07, 0xff),
1259 	 * 0x01, VsmpsCSysClkReq1HPValid
1260 	 * 0x02, VarmSysClkReq1HPValid
1261 	 * 0x04, VbbSysClkReq1HPValid
1262 	 * 0x08, VsmpsMSysClkReq1HPValid
1264 	REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2,	0x03, 0x08, 0x0f),
1266 	 * 0x01, VsmpsAHwHPReq1Valid
1267 	 * 0x02, VsmpsBHwHPReq1Valid
1268 	 * 0x04, VsafeHwHPReq1Valid
1269 	 * 0x08, VanaHwHPReq1Valid
1270 	 * 0x10, VpllHwHPReq1Valid
1271 	 * 0x20, Vaux1HwHPReq1Valid
1272 	 * 0x40, Vaux2HwHPReq1Valid
1273 	 * 0x80, Vaux3HwHPReq1Valid
1275 	REG_INIT(AB8505_REGUHWHPREQ1VALID1,	0x03, 0x09, 0xff),
1277 	 * 0x08, VsmpsMHwHPReq1Valid
1279 	REG_INIT(AB8505_REGUHWHPREQ1VALID2,	0x03, 0x0a, 0x08),
1281 	 * 0x01, VsmpsAHwHPReq2Valid
1282 	 * 0x02, VsmpsBHwHPReq2Valid
1283 	 * 0x04, VsafeHwHPReq2Valid
1284 	 * 0x08, VanaHwHPReq2Valid
1285 	 * 0x10, VpllHwHPReq2Valid
1286 	 * 0x20, Vaux1HwHPReq2Valid
1287 	 * 0x40, Vaux2HwHPReq2Valid
1288 	 * 0x80, Vaux3HwHPReq2Valid
1290 	REG_INIT(AB8505_REGUHWHPREQ2VALID1,	0x03, 0x0b, 0xff),
1292 	 * 0x08, VsmpsMHwHPReq2Valid
1294 	REG_INIT(AB8505_REGUHWHPREQ2VALID2,	0x03, 0x0c, 0x08),
1296 	 * 0x01, VsmpsCSwHPReqValid
1297 	 * 0x02, VarmSwHPReqValid
1298 	 * 0x04, VsmpsASwHPReqValid
1299 	 * 0x08, VsmpsBSwHPReqValid
1300 	 * 0x10, VsafeSwHPReqValid
1301 	 * 0x20, VanaSwHPReqValid
1302 	 * 0x40, VpllSwHPReqValid
1303 	 * 0x80, Vaux1SwHPReqValid
1305 	REG_INIT(AB8505_REGUSWHPREQVALID1,	0x03, 0x0d, 0xff),
1307 	 * 0x01, Vaux2SwHPReqValid
1308 	 * 0x02, Vaux3SwHPReqValid
1309 	 * 0x20, VsmpsMSwHPReqValid
1311 	REG_INIT(AB8505_REGUSWHPREQVALID2,	0x03, 0x0e, 0x23),
1313 	 * 0x02, SysClkReq2Valid1
1314 	 * 0x04, SysClkReq3Valid1
1315 	 * 0x08, SysClkReq4Valid1
1317 	REG_INIT(AB8505_REGUSYSCLKREQVALID1,	0x03, 0x0f, 0x0e),
1319 	 * 0x02, SysClkReq2Valid2
1320 	 * 0x04, SysClkReq3Valid2
1321 	 * 0x08, SysClkReq4Valid2
1323 	REG_INIT(AB8505_REGUSYSCLKREQVALID2,	0x03, 0x10, 0x0e),
1325 	 * 0x01, Vaux4SwHPReqValid
1326 	 * 0x02, Vaux4HwHPReq2Valid
1327 	 * 0x04, Vaux4HwHPReq1Valid
1328 	 * 0x08, Vaux4SysClkReq1HPValid
1330 	REG_INIT(AB8505_REGUVAUX4REQVALID,	0x03, 0x11, 0x0f),
1332 	 * 0x02, VadcEna
1333 	 * 0x04, VintCore12Ena
1334 	 * 0x38, VintCore12Sel
1335 	 * 0x40, VintCore12LP
1336 	 * 0x80, VadcLP
1338 	REG_INIT(AB8505_REGUMISC1,		0x03, 0x80, 0xfe),
1340 	 * 0x02, VaudioEna
1341 	 * 0x04, VdmicEna
1342 	 * 0x08, Vamic1Ena
1343 	 * 0x10, Vamic2Ena
1345 	REG_INIT(AB8505_VAUDIOSUPPLY,		0x03, 0x83, 0x1e),
1347 	 * 0x01, Vamic1_dzout
1348 	 * 0x02, Vamic2_dzout
1350 	REG_INIT(AB8505_REGUCTRL1VAMIC,		0x03, 0x84, 0x03),
1352 	 * 0x03, VsmpsARegu
1353 	 * 0x0c, VsmpsASelCtrl
1354 	 * 0x10, VsmpsAAutoMode
1355 	 * 0x20, VsmpsAPWMMode
1357 	REG_INIT(AB8505_VSMPSAREGU,		0x04, 0x03, 0x3f),
1359 	 * 0x03, VsmpsBRegu
1360 	 * 0x0c, VsmpsBSelCtrl
1361 	 * 0x10, VsmpsBAutoMode
1362 	 * 0x20, VsmpsBPWMMode
1364 	REG_INIT(AB8505_VSMPSBREGU,		0x04, 0x04, 0x3f),
1366 	 * 0x03, VsafeRegu
1367 	 * 0x0c, VsafeSelCtrl
1368 	 * 0x10, VsafeAutoMode
1369 	 * 0x20, VsafePWMMode
1371 	REG_INIT(AB8505_VSAFEREGU,		0x04, 0x05, 0x3f),
1373 	 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1374 	 * 0x0c, VanaRegu
1376 	REG_INIT(AB8505_VPLLVANAREGU,		0x04, 0x06, 0x0f),
1378 	 * 0x03, VextSupply1Regu
1379 	 * 0x0c, VextSupply2Regu
1380 	 * 0x30, VextSupply3Regu
1381 	 * 0x40, ExtSupply2Bypass
1382 	 * 0x80, ExtSupply3Bypass
1384 	REG_INIT(AB8505_EXTSUPPLYREGU,		0x04, 0x08, 0xff),
1386 	 * 0x03, Vaux1Regu
1387 	 * 0x0c, Vaux2Regu
1389 	REG_INIT(AB8505_VAUX12REGU,		0x04, 0x09, 0x0f),
1391 	 * 0x0f, Vaux3Regu
1393 	REG_INIT(AB8505_VRF1VAUX3REGU,		0x04, 0x0a, 0x0f),
1395 	 * 0x3f, VsmpsASel1
1397 	REG_INIT(AB8505_VSMPSASEL1,		0x04, 0x13, 0x3f),
1399 	 * 0x3f, VsmpsASel2
1401 	REG_INIT(AB8505_VSMPSASEL2,		0x04, 0x14, 0x3f),
1403 	 * 0x3f, VsmpsASel3
1405 	REG_INIT(AB8505_VSMPSASEL3,		0x04, 0x15, 0x3f),
1407 	 * 0x3f, VsmpsBSel1
1409 	REG_INIT(AB8505_VSMPSBSEL1,		0x04, 0x17, 0x3f),
1411 	 * 0x3f, VsmpsBSel2
1413 	REG_INIT(AB8505_VSMPSBSEL2,		0x04, 0x18, 0x3f),
1415 	 * 0x3f, VsmpsBSel3
1417 	REG_INIT(AB8505_VSMPSBSEL3,		0x04, 0x19, 0x3f),
1419 	 * 0x7f, VsafeSel1
1421 	REG_INIT(AB8505_VSAFESEL1,		0x04, 0x1b, 0x7f),
1423 	 * 0x3f, VsafeSel2
1425 	REG_INIT(AB8505_VSAFESEL2,		0x04, 0x1c, 0x7f),
1427 	 * 0x3f, VsafeSel3
1429 	REG_INIT(AB8505_VSAFESEL3,		0x04, 0x1d, 0x7f),
1431 	 * 0x0f, Vaux1Sel
1433 	REG_INIT(AB8505_VAUX1SEL,		0x04, 0x1f, 0x0f),
1435 	 * 0x0f, Vaux2Sel
1437 	REG_INIT(AB8505_VAUX2SEL,		0x04, 0x20, 0x0f),
1439 	 * 0x07, Vaux3Sel
1440 	 * 0x30, VRF1Sel
1442 	REG_INIT(AB8505_VRF1VAUX3SEL,		0x04, 0x21, 0x37),
1444 	 * 0x03, Vaux4RequestCtrl
1446 	REG_INIT(AB8505_VAUX4REQCTRL,		0x04, 0x2d, 0x03),
1448 	 * 0x03, Vaux4Regu
1450 	REG_INIT(AB8505_VAUX4REGU,		0x04, 0x2e, 0x03),
1452 	 * 0x0f, Vaux4Sel
1454 	REG_INIT(AB8505_VAUX4SEL,		0x04, 0x2f, 0x0f),
1456 	 * 0x04, Vaux1Disch
1457 	 * 0x08, Vaux2Disch
1458 	 * 0x10, Vaux3Disch
1459 	 * 0x20, Vintcore12Disch
1460 	 * 0x40, VTVoutDisch
1461 	 * 0x80, VaudioDisch
1463 	REG_INIT(AB8505_REGUCTRLDISCH,		0x04, 0x43, 0xfc),
1465 	 * 0x02, VanaDisch
1466 	 * 0x04, VdmicPullDownEna
1467 	 * 0x10, VdmicDisch
1469 	REG_INIT(AB8505_REGUCTRLDISCH2,		0x04, 0x44, 0x16),
1471 	 * 0x01, Vaux4Disch
1473 	REG_INIT(AB8505_REGUCTRLDISCH3,		0x04, 0x48, 0x01),
1475 	 * 0x07, Vaux5Sel
1476 	 * 0x08, Vaux5LP
1477 	 * 0x10, Vaux5Ena
1478 	 * 0x20, Vaux5Disch
1479 	 * 0x40, Vaux5DisSfst
1480 	 * 0x80, Vaux5DisPulld
1482 	REG_INIT(AB8505_CTRLVAUX5,		0x01, 0x55, 0xff),
1484 	 * 0x07, Vaux6Sel
1485 	 * 0x08, Vaux6LP
1486 	 * 0x10, Vaux6Ena
1487 	 * 0x80, Vaux6DisPulld
1489 	REG_INIT(AB8505_CTRLVAUX6,		0x01, 0x56, 0x9f),
1567 	/* fix for hardware before ab8500v2.0 */  in ab8500_regulator_register()
1573 			info->voltage_mask = 0xf;  in ab8500_regulator_register()
1585 	return 0;  in ab8500_regulator_register()
1605 	if (err < 0) {  in ab8500_regulator_probe()
1612 	for (i = 0; i < abx500_regulator.info_size; i++) {  in ab8500_regulator_probe()
1619 	return 0;  in ab8500_regulator_probe()
1634 	if (ret != 0)  in ab8500_regulator_init()