1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * EHRPWM PWM driver
5  * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
10 #include <linux/pwm.h>
94 #define NUM_PWM_CHANNEL		2	/* EHRPWM channels */
133 static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask,  in ehrpwm_modify()  argument
139 	val &= ~mask;  in ehrpwm_modify()
140 	val |= value & mask;  in ehrpwm_modify()
145  * set_prescale_div -	Set up the prescaler divider function
187 	 * Configure PWM output to HIGH/LOW level on counter  in configure_polarity()
196 		if (pc->polarity[chan] == PWM_POLARITY_INVERSED)  in configure_polarity()
204 		if (pc->polarity[chan] == PWM_POLARITY_INVERSED)  in configure_polarity()
211 	ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);  in configure_polarity()
218 static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,  in ehrpwm_pwm_config()  argument
228 		return -ERANGE;  in ehrpwm_pwm_config()
230 	c = pc->clk_rate;  in ehrpwm_pwm_config()
239 		c = pc->clk_rate;  in ehrpwm_pwm_config()
246 	 * Period values should be same for multiple PWM channels as IP uses  in ehrpwm_pwm_config()
247 	 * same period register for multiple channels.  in ehrpwm_pwm_config()
250 		if (pc->period_cycles[i] &&  in ehrpwm_pwm_config()
251 				(pc->period_cycles[i] != period_cycles)) {  in ehrpwm_pwm_config()
254 			 * channels being configured.  in ehrpwm_pwm_config()
256 			if (i == pwm->hwpwm)  in ehrpwm_pwm_config()
259 			dev_err(chip->dev,  in ehrpwm_pwm_config()
262 			return -EINVAL;  in ehrpwm_pwm_config()
266 	pc->period_cycles[pwm->hwpwm] = period_cycles;  in ehrpwm_pwm_config()
268 	/* Configure clock prescaler to support Low frequency PWM wave */  in ehrpwm_pwm_config()
271 		dev_err(chip->dev, "Unsupported values\n");  in ehrpwm_pwm_config()
272 		return -EINVAL;  in ehrpwm_pwm_config()
275 	pm_runtime_get_sync(chip->dev);  in ehrpwm_pwm_config()
278 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);  in ehrpwm_pwm_config()
285 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);  in ehrpwm_pwm_config()
287 	ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);  in ehrpwm_pwm_config()
289 	/* Configure ehrpwm counter for up-count mode */  in ehrpwm_pwm_config()
290 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,  in ehrpwm_pwm_config()
293 	if (pwm->hwpwm == 1)  in ehrpwm_pwm_config()
300 	ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);  in ehrpwm_pwm_config()
302 	pm_runtime_put_sync(chip->dev);  in ehrpwm_pwm_config()
308 				   struct pwm_device *pwm,  in ehrpwm_pwm_set_polarity()  argument
314 	pc->polarity[pwm->hwpwm] = polarity;  in ehrpwm_pwm_set_polarity()
319 static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)  in ehrpwm_pwm_enable()  argument
325 	/* Leave clock enabled on enabling PWM */  in ehrpwm_pwm_enable()
326 	pm_runtime_get_sync(chip->dev);  in ehrpwm_pwm_enable()
328 	/* Disabling Action Qualifier on PWM output */  in ehrpwm_pwm_enable()
329 	if (pwm->hwpwm) {  in ehrpwm_pwm_enable()
338 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_enable()
341 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_enable()
343 	/* Channels polarity can be configured from action qualifier module */  in ehrpwm_pwm_enable()
344 	configure_polarity(pc, pwm->hwpwm);  in ehrpwm_pwm_enable()
347 	ret = clk_enable(pc->tbclk);  in ehrpwm_pwm_enable()
349 		dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",  in ehrpwm_pwm_enable()
350 			dev_name(pc->chip.dev), ret);  in ehrpwm_pwm_enable()
357 static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)  in ehrpwm_pwm_disable()  argument
362 	/* Action Qualifier puts PWM output low forcefully */  in ehrpwm_pwm_disable()
363 	if (pwm->hwpwm) {  in ehrpwm_pwm_disable()
372 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_disable()
374 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_disable()
377 	 * Action Qualifier control on PWM output from next TBCLK  in ehrpwm_pwm_disable()
379 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_disable()
382 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_disable()
384 	/* Disabling TBCLK on PWM disable */  in ehrpwm_pwm_disable()
385 	clk_disable(pc->tbclk);  in ehrpwm_pwm_disable()
387 	/* Disable clock on PWM disable */  in ehrpwm_pwm_disable()
388 	pm_runtime_put_sync(chip->dev);  in ehrpwm_pwm_disable()
391 static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)  in ehrpwm_pwm_free()  argument
395 	if (pwm_is_enabled(pwm)) {  in ehrpwm_pwm_free()
396 		dev_warn(chip->dev, "Removing PWM device without disabling\n");  in ehrpwm_pwm_free()
397 		pm_runtime_put_sync(chip->dev);  in ehrpwm_pwm_free()
401 	pc->period_cycles[pwm->hwpwm] = 0;  in ehrpwm_pwm_free()
414 	{ .compatible = "ti,am3352-ehrpwm" },
415 	{ .compatible = "ti,am33xx-ehrpwm" },
422 	struct device_node *np = pdev->dev.of_node;  in ehrpwm_pwm_probe()
428 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);  in ehrpwm_pwm_probe()
430 		return -ENOMEM;  in ehrpwm_pwm_probe()
432 	clk = devm_clk_get(&pdev->dev, "fck");  in ehrpwm_pwm_probe()
434 		if (of_device_is_compatible(np, "ti,am33xx-ecap")) {  in ehrpwm_pwm_probe()
435 			dev_warn(&pdev->dev, "Binding is obsolete.\n");  in ehrpwm_pwm_probe()
436 			clk = devm_clk_get(pdev->dev.parent, "fck");  in ehrpwm_pwm_probe()
441 		dev_err(&pdev->dev, "failed to get clock\n");  in ehrpwm_pwm_probe()
445 	pc->clk_rate = clk_get_rate(clk);  in ehrpwm_pwm_probe()
446 	if (!pc->clk_rate) {  in ehrpwm_pwm_probe()
447 		dev_err(&pdev->dev, "failed to get clock rate\n");  in ehrpwm_pwm_probe()
448 		return -EINVAL;  in ehrpwm_pwm_probe()
451 	pc->chip.dev = &pdev->dev;  in ehrpwm_pwm_probe()
452 	pc->chip.ops = &ehrpwm_pwm_ops;  in ehrpwm_pwm_probe()
453 	pc->chip.of_xlate = of_pwm_xlate_with_flags;  in ehrpwm_pwm_probe()
454 	pc->chip.of_pwm_n_cells = 3;  in ehrpwm_pwm_probe()
455 	pc->chip.base = -1;  in ehrpwm_pwm_probe()
456 	pc->chip.npwm = NUM_PWM_CHANNEL;  in ehrpwm_pwm_probe()
459 	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);  in ehrpwm_pwm_probe()
460 	if (IS_ERR(pc->mmio_base))  in ehrpwm_pwm_probe()
461 		return PTR_ERR(pc->mmio_base);  in ehrpwm_pwm_probe()
464 	pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");  in ehrpwm_pwm_probe()
465 	if (IS_ERR(pc->tbclk)) {  in ehrpwm_pwm_probe()
466 		dev_err(&pdev->dev, "Failed to get tbclk\n");  in ehrpwm_pwm_probe()
467 		return PTR_ERR(pc->tbclk);  in ehrpwm_pwm_probe()
470 	ret = clk_prepare(pc->tbclk);  in ehrpwm_pwm_probe()
472 		dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);  in ehrpwm_pwm_probe()
476 	ret = pwmchip_add(&pc->chip);  in ehrpwm_pwm_probe()
478 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);  in ehrpwm_pwm_probe()
483 	pm_runtime_enable(&pdev->dev);  in ehrpwm_pwm_probe()
488 	clk_unprepare(pc->tbclk);  in ehrpwm_pwm_probe()
497 	clk_unprepare(pc->tbclk);  in ehrpwm_pwm_remove()
499 	pm_runtime_disable(&pdev->dev);  in ehrpwm_pwm_remove()
501 	return pwmchip_remove(&pc->chip);  in ehrpwm_pwm_remove()
507 	pm_runtime_get_sync(pc->chip.dev);  in ehrpwm_pwm_save_context()
509 	pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);  in ehrpwm_pwm_save_context()
510 	pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);  in ehrpwm_pwm_save_context()
511 	pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);  in ehrpwm_pwm_save_context()
512 	pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);  in ehrpwm_pwm_save_context()
513 	pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);  in ehrpwm_pwm_save_context()
514 	pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);  in ehrpwm_pwm_save_context()
515 	pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);  in ehrpwm_pwm_save_context()
516 	pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);  in ehrpwm_pwm_save_context()
518 	pm_runtime_put_sync(pc->chip.dev);  in ehrpwm_pwm_save_context()
523 	ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);  in ehrpwm_pwm_restore_context()
524 	ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);  in ehrpwm_pwm_restore_context()
525 	ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);  in ehrpwm_pwm_restore_context()
526 	ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);  in ehrpwm_pwm_restore_context()
527 	ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);  in ehrpwm_pwm_restore_context()
528 	ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);  in ehrpwm_pwm_restore_context()
529 	ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);  in ehrpwm_pwm_restore_context()
530 	ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);  in ehrpwm_pwm_restore_context()
540 	for (i = 0; i < pc->chip.npwm; i++) {  in ehrpwm_pwm_suspend()
541 		struct pwm_device *pwm = &pc->chip.pwms[i];  in ehrpwm_pwm_suspend()  local
543 		if (!pwm_is_enabled(pwm))  in ehrpwm_pwm_suspend()
546 		/* Disable explicitly if PWM is running */  in ehrpwm_pwm_suspend()
558 	for (i = 0; i < pc->chip.npwm; i++) {  in ehrpwm_pwm_resume()
559 		struct pwm_device *pwm = &pc->chip.pwms[i];  in ehrpwm_pwm_resume()  local
561 		if (!pwm_is_enabled(pwm))  in ehrpwm_pwm_resume()
564 		/* Enable explicitly if PWM was running */  in ehrpwm_pwm_resume()
588 MODULE_DESCRIPTION("EHRPWM PWM driver");