Lines Matching +full:sun50i +full:- +full:h6 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
22 #include <linux/pwm.h>
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
103 return readl(chip->base + offset); in sun4i_pwm_readl()
109 writel(val, chip->base + offset); in sun4i_pwm_writel()
113 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
121 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
126 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
131 sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_get_state()
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); in sun4i_pwm_get_state()
134 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
135 state->enabled = true; in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
140 sun4i_pwm->data->has_prescaler_bypass) in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
149 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
151 state->polarity = PWM_POLARITY_INVERSED; in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
155 state->enabled = true; in sun4i_pwm_get_state()
157 state->enabled = false; in sun4i_pwm_get_state()
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
176 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
178 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
179 state->enabled && in sun4i_pwm_calculate()
180 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
181 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
182 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); in sun4i_pwm_calculate()
188 if (sun4i_pwm->data->has_prescaler_bypass) { in sun4i_pwm_calculate()
196 div = clk_rate * state->period + NSEC_PER_SEC / 2; in sun4i_pwm_calculate()
198 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
212 div = div * state->period; in sun4i_pwm_calculate()
214 if (div - 1 <= PWM_PRD_MASK) in sun4i_pwm_calculate()
218 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
219 return -EINVAL; in sun4i_pwm_calculate()
223 div *= state->duty_cycle; in sun4i_pwm_calculate()
224 do_div(div, state->period); in sun4i_pwm_calculate()
231 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in sun4i_pwm_apply() argument
242 pwm_get_state(pwm, &cstate); in sun4i_pwm_apply()
245 ret = clk_prepare_enable(sun4i_pwm->clk); in sun4i_pwm_apply()
247 dev_err(chip->dev, "failed to enable PWM clock\n"); in sun4i_pwm_apply()
255 dev_err(chip->dev, "period exceeds the maximum value\n"); in sun4i_pwm_apply()
257 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
261 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
264 if (sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_apply()
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
269 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
278 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
281 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); in sun4i_pwm_apply()
282 ctrl |= BIT_CH(prescaler, pwm->hwpwm); in sun4i_pwm_apply()
286 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_apply()
287 sun4i_pwm->next_period[pwm->hwpwm] = jiffies + in sun4i_pwm_apply()
290 if (state->polarity != PWM_POLARITY_NORMAL) in sun4i_pwm_apply()
291 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
293 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
295 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
297 if (state->enabled) { in sun4i_pwm_apply()
298 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
300 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
301 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
306 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
308 if (state->enabled) in sun4i_pwm_apply()
313 if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) { in sun4i_pwm_apply()
314 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] - in sun4i_pwm_apply()
322 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
324 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
325 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
327 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
329 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
369 .compatible = "allwinner,sun4i-a10-pwm",
372 .compatible = "allwinner,sun5i-a10s-pwm",
375 .compatible = "allwinner,sun5i-a13-pwm",
378 .compatible = "allwinner,sun7i-a20-pwm",
381 .compatible = "allwinner,sun8i-h3-pwm",
384 .compatible = "allwinner,sun50i-a64-pwm",
387 .compatible = "allwinner,sun50i-h6-pwm",
397 struct sun4i_pwm_chip *pwm; in sun4i_pwm_probe() local
401 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); in sun4i_pwm_probe()
402 if (!pwm) in sun4i_pwm_probe()
403 return -ENOMEM; in sun4i_pwm_probe()
405 pwm->data = of_device_get_match_data(&pdev->dev); in sun4i_pwm_probe()
406 if (!pwm->data) in sun4i_pwm_probe()
407 return -ENODEV; in sun4i_pwm_probe()
410 pwm->base = devm_ioremap_resource(&pdev->dev, res); in sun4i_pwm_probe()
411 if (IS_ERR(pwm->base)) in sun4i_pwm_probe()
412 return PTR_ERR(pwm->base); in sun4i_pwm_probe()
418 * Some variants (e.g. H6) need another clock to access the in sun4i_pwm_probe()
422 * unnamed one of the PWM device) and if this is not found we fall in sun4i_pwm_probe()
423 * back to the first clock of the PWM. in sun4i_pwm_probe()
425 pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); in sun4i_pwm_probe()
426 if (IS_ERR(pwm->clk)) in sun4i_pwm_probe()
427 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk), in sun4i_pwm_probe()
430 if (!pwm->clk) { in sun4i_pwm_probe()
431 pwm->clk = devm_clk_get(&pdev->dev, NULL); in sun4i_pwm_probe()
432 if (IS_ERR(pwm->clk)) in sun4i_pwm_probe()
433 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk), in sun4i_pwm_probe()
437 pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); in sun4i_pwm_probe()
438 if (IS_ERR(pwm->bus_clk)) in sun4i_pwm_probe()
439 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk), in sun4i_pwm_probe()
442 pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in sun4i_pwm_probe()
443 if (IS_ERR(pwm->rst)) in sun4i_pwm_probe()
444 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->rst), in sun4i_pwm_probe()
448 ret = reset_control_deassert(pwm->rst); in sun4i_pwm_probe()
450 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", in sun4i_pwm_probe()
459 ret = clk_prepare_enable(pwm->bus_clk); in sun4i_pwm_probe()
461 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", in sun4i_pwm_probe()
466 pwm->chip.dev = &pdev->dev; in sun4i_pwm_probe()
467 pwm->chip.ops = &sun4i_pwm_ops; in sun4i_pwm_probe()
468 pwm->chip.base = -1; in sun4i_pwm_probe()
469 pwm->chip.npwm = pwm->data->npwm; in sun4i_pwm_probe()
470 pwm->chip.of_xlate = of_pwm_xlate_with_flags; in sun4i_pwm_probe()
471 pwm->chip.of_pwm_n_cells = 3; in sun4i_pwm_probe()
473 spin_lock_init(&pwm->ctrl_lock); in sun4i_pwm_probe()
475 ret = pwmchip_add(&pwm->chip); in sun4i_pwm_probe()
477 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); in sun4i_pwm_probe()
481 platform_set_drvdata(pdev, pwm); in sun4i_pwm_probe()
486 clk_disable_unprepare(pwm->bus_clk); in sun4i_pwm_probe()
488 reset_control_assert(pwm->rst); in sun4i_pwm_probe()
495 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); in sun4i_pwm_remove() local
498 ret = pwmchip_remove(&pwm->chip); in sun4i_pwm_remove()
502 clk_disable_unprepare(pwm->bus_clk); in sun4i_pwm_remove()
503 reset_control_assert(pwm->rst); in sun4i_pwm_remove()
510 .name = "sun4i-pwm",
518 MODULE_ALIAS("platform:sun4i-pwm");
519 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
520 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");