Lines Matching +full:rk3288 +full:- +full:vop
1 // SPDX-License-Identifier: GPL-2.0-only
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
77 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
78 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
81 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
82 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
83 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
85 val = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_get_state()
86 state->enabled = (val & enable_conf) == enable_conf; in rockchip_pwm_get_state()
88 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) in rockchip_pwm_get_state()
89 state->polarity = PWM_POLARITY_INVERSED; in rockchip_pwm_get_state()
91 state->polarity = PWM_POLARITY_NORMAL; in rockchip_pwm_get_state()
93 clk_disable(pc->pclk); in rockchip_pwm_get_state()
104 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_config()
111 div = clk_rate * state->period; in rockchip_pwm_config()
113 pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
115 div = clk_rate * state->duty_cycle; in rockchip_pwm_config()
116 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
122 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_config()
123 if (pc->data->supports_lock) { in rockchip_pwm_config()
125 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); in rockchip_pwm_config()
128 writel(period, pc->base + pc->data->regs.period); in rockchip_pwm_config()
129 writel(duty, pc->base + pc->data->regs.duty); in rockchip_pwm_config()
131 if (pc->data->supports_polarity) { in rockchip_pwm_config()
133 if (state->polarity == PWM_POLARITY_INVERSED) in rockchip_pwm_config()
144 if (pc->data->supports_lock) in rockchip_pwm_config()
147 writel(ctrl, pc->base + pc->data->regs.ctrl); in rockchip_pwm_config()
155 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_enable()
160 ret = clk_enable(pc->clk); in rockchip_pwm_enable()
165 val = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_enable()
172 writel_relaxed(val, pc->base + pc->data->regs.ctrl); in rockchip_pwm_enable()
175 clk_disable(pc->clk); in rockchip_pwm_enable()
188 ret = clk_enable(pc->pclk); in rockchip_pwm_apply()
195 if (state->polarity != curstate.polarity && enabled && in rockchip_pwm_apply()
196 !pc->data->supports_lock) { in rockchip_pwm_apply()
204 if (state->enabled != enabled) { in rockchip_pwm_apply()
205 ret = rockchip_pwm_enable(chip, pwm, state->enabled); in rockchip_pwm_apply()
211 clk_disable(pc->pclk); in rockchip_pwm_apply()
278 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
279 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
280 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
281 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
294 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); in rockchip_pwm_probe()
296 return -EINVAL; in rockchip_pwm_probe()
298 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); in rockchip_pwm_probe()
300 return -ENOMEM; in rockchip_pwm_probe()
303 pc->base = devm_ioremap_resource(&pdev->dev, r); in rockchip_pwm_probe()
304 if (IS_ERR(pc->base)) in rockchip_pwm_probe()
305 return PTR_ERR(pc->base); in rockchip_pwm_probe()
307 pc->clk = devm_clk_get(&pdev->dev, "pwm"); in rockchip_pwm_probe()
308 if (IS_ERR(pc->clk)) { in rockchip_pwm_probe()
309 pc->clk = devm_clk_get(&pdev->dev, NULL); in rockchip_pwm_probe()
310 if (IS_ERR(pc->clk)) in rockchip_pwm_probe()
311 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), in rockchip_pwm_probe()
315 count = of_count_phandle_with_args(pdev->dev.of_node, in rockchip_pwm_probe()
316 "clocks", "#clock-cells"); in rockchip_pwm_probe()
318 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); in rockchip_pwm_probe()
320 pc->pclk = pc->clk; in rockchip_pwm_probe()
322 if (IS_ERR(pc->pclk)) { in rockchip_pwm_probe()
323 ret = PTR_ERR(pc->pclk); in rockchip_pwm_probe()
324 if (ret != -EPROBE_DEFER) in rockchip_pwm_probe()
325 dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret); in rockchip_pwm_probe()
329 ret = clk_prepare_enable(pc->clk); in rockchip_pwm_probe()
331 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret); in rockchip_pwm_probe()
335 ret = clk_prepare(pc->pclk); in rockchip_pwm_probe()
337 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret); in rockchip_pwm_probe()
343 pc->data = id->data; in rockchip_pwm_probe()
344 pc->chip.dev = &pdev->dev; in rockchip_pwm_probe()
345 pc->chip.ops = &rockchip_pwm_ops; in rockchip_pwm_probe()
346 pc->chip.base = -1; in rockchip_pwm_probe()
347 pc->chip.npwm = 1; in rockchip_pwm_probe()
349 if (pc->data->supports_polarity) { in rockchip_pwm_probe()
350 pc->chip.of_xlate = of_pwm_xlate_with_flags; in rockchip_pwm_probe()
351 pc->chip.of_pwm_n_cells = 3; in rockchip_pwm_probe()
354 ret = pwmchip_add(&pc->chip); in rockchip_pwm_probe()
356 clk_unprepare(pc->clk); in rockchip_pwm_probe()
357 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); in rockchip_pwm_probe()
362 enable_conf = pc->data->enable_conf; in rockchip_pwm_probe()
363 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_probe()
365 clk_disable(pc->clk); in rockchip_pwm_probe()
370 clk_unprepare(pc->pclk); in rockchip_pwm_probe()
372 clk_disable_unprepare(pc->clk); in rockchip_pwm_probe()
392 if (pwm_is_enabled(pc->chip.pwms)) in rockchip_pwm_remove()
393 clk_disable(pc->clk); in rockchip_pwm_remove()
395 clk_unprepare(pc->pclk); in rockchip_pwm_remove()
396 clk_unprepare(pc->clk); in rockchip_pwm_remove()
398 return pwmchip_remove(&pc->chip); in rockchip_pwm_remove()
403 .name = "rockchip-pwm",