Lines Matching +full:tpu +full:- +full:r8a7740
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
72 struct tpu_device *tpu; member
73 unsigned int channel; /* Channel number in the TPU */
94 void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
95 + pwm->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
105 dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
106 pwm->channel, states[state]); in tpu_pwm_set_pin()
111 pwm->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
116 pwm->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
121 pwm->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
132 spin_lock_irqsave(&pwm->tpu->lock, flags); in tpu_pwm_start_stop()
133 value = ioread16(pwm->tpu->base + TPU_TSTR); in tpu_pwm_start_stop()
136 value |= 1 << pwm->channel; in tpu_pwm_start_stop()
138 value &= ~(1 << pwm->channel); in tpu_pwm_start_stop()
140 iowrite16(value, pwm->tpu->base + TPU_TSTR); in tpu_pwm_start_stop()
141 spin_unlock_irqrestore(&pwm->tpu->lock, flags); in tpu_pwm_start_stop()
148 if (!pwm->timer_on) { in tpu_pwm_timer_start()
150 pm_runtime_get_sync(&pwm->tpu->pdev->dev); in tpu_pwm_timer_start()
151 ret = clk_prepare_enable(pwm->tpu->clk); in tpu_pwm_timer_start()
153 dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n"); in tpu_pwm_timer_start()
156 pwm->timer_on = true; in tpu_pwm_timer_start()
168 * - Clear TCNT on TGRB match in tpu_pwm_timer_start()
169 * - Count on rising edge in tpu_pwm_timer_start()
170 * - Set prescaler in tpu_pwm_timer_start()
171 * - Output 0 until TGRA, output 1 until TGRB (active low polarity) in tpu_pwm_timer_start()
172 * - Output 1 until TGRA, output 0 until TGRB (active high polarity in tpu_pwm_timer_start()
173 * - PWM mode in tpu_pwm_timer_start()
176 pwm->prescaler); in tpu_pwm_timer_start()
179 tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); in tpu_pwm_timer_start()
180 tpu_pwm_write(pwm, TPU_TGRBn, pwm->period); in tpu_pwm_timer_start()
182 dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", in tpu_pwm_timer_start()
183 pwm->channel, pwm->duty, pwm->period); in tpu_pwm_timer_start()
193 if (!pwm->timer_on) in tpu_pwm_timer_stop()
200 clk_disable_unprepare(pwm->tpu->clk); in tpu_pwm_timer_stop()
201 pm_runtime_put(&pwm->tpu->pdev->dev); in tpu_pwm_timer_stop()
203 pwm->timer_on = false; in tpu_pwm_timer_stop()
206 /* -----------------------------------------------------------------------------
212 struct tpu_device *tpu = to_tpu_device(chip); in tpu_pwm_request() local
215 if (_pwm->hwpwm >= TPU_CHANNEL_MAX) in tpu_pwm_request()
216 return -EINVAL; in tpu_pwm_request()
220 return -ENOMEM; in tpu_pwm_request()
222 pwm->tpu = tpu; in tpu_pwm_request()
223 pwm->channel = _pwm->hwpwm; in tpu_pwm_request()
224 pwm->polarity = PWM_POLARITY_NORMAL; in tpu_pwm_request()
225 pwm->prescaler = 0; in tpu_pwm_request()
226 pwm->period = 0; in tpu_pwm_request()
227 pwm->duty = 0; in tpu_pwm_request()
229 pwm->timer_on = false; in tpu_pwm_request()
249 struct tpu_device *tpu = to_tpu_device(chip); in tpu_pwm_config() local
261 clk_rate = clk_get_rate(tpu->clk); in tpu_pwm_config()
271 dev_err(&tpu->pdev->dev, "clock rate mismatch\n"); in tpu_pwm_config()
272 return -ENOTSUPP; in tpu_pwm_config()
279 return -EINVAL; in tpu_pwm_config()
284 dev_dbg(&tpu->pdev->dev, in tpu_pwm_config()
288 if (pwm->prescaler == prescaler && pwm->period == period) in tpu_pwm_config()
291 pwm->prescaler = prescaler; in tpu_pwm_config()
292 pwm->period = period; in tpu_pwm_config()
293 pwm->duty = duty; in tpu_pwm_config()
299 if (duty_only && pwm->timer_on) { in tpu_pwm_config()
305 tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty); in tpu_pwm_config()
306 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel, in tpu_pwm_config()
307 pwm->duty); in tpu_pwm_config()
332 pwm->polarity = polarity; in tpu_pwm_set_polarity()
350 if (pwm->duty == 0 || pwm->duty == pwm->period) { in tpu_pwm_enable()
351 tpu_pwm_set_pin(pwm, pwm->duty ? in tpu_pwm_enable()
379 /* -----------------------------------------------------------------------------
385 struct tpu_device *tpu; in tpu_probe() local
389 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); in tpu_probe()
390 if (tpu == NULL) in tpu_probe()
391 return -ENOMEM; in tpu_probe()
393 spin_lock_init(&tpu->lock); in tpu_probe()
394 tpu->pdev = pdev; in tpu_probe()
398 tpu->base = devm_ioremap_resource(&pdev->dev, res); in tpu_probe()
399 if (IS_ERR(tpu->base)) in tpu_probe()
400 return PTR_ERR(tpu->base); in tpu_probe()
402 tpu->clk = devm_clk_get(&pdev->dev, NULL); in tpu_probe()
403 if (IS_ERR(tpu->clk)) { in tpu_probe()
404 dev_err(&pdev->dev, "cannot get clock\n"); in tpu_probe()
405 return PTR_ERR(tpu->clk); in tpu_probe()
409 platform_set_drvdata(pdev, tpu); in tpu_probe()
411 tpu->chip.dev = &pdev->dev; in tpu_probe()
412 tpu->chip.ops = &tpu_pwm_ops; in tpu_probe()
413 tpu->chip.of_xlate = of_pwm_xlate_with_flags; in tpu_probe()
414 tpu->chip.of_pwm_n_cells = 3; in tpu_probe()
415 tpu->chip.base = -1; in tpu_probe()
416 tpu->chip.npwm = TPU_CHANNEL_MAX; in tpu_probe()
418 pm_runtime_enable(&pdev->dev); in tpu_probe()
420 ret = pwmchip_add(&tpu->chip); in tpu_probe()
422 dev_err(&pdev->dev, "failed to register PWM chip\n"); in tpu_probe()
423 pm_runtime_disable(&pdev->dev); in tpu_probe()
432 struct tpu_device *tpu = platform_get_drvdata(pdev); in tpu_remove() local
435 ret = pwmchip_remove(&tpu->chip); in tpu_remove()
437 pm_runtime_disable(&pdev->dev); in tpu_remove()
444 { .compatible = "renesas,tpu-r8a73a4", },
445 { .compatible = "renesas,tpu-r8a7740", },
446 { .compatible = "renesas,tpu-r8a7790", },
447 { .compatible = "renesas,tpu", },
458 .name = "renesas-tpu-pwm",
466 MODULE_DESCRIPTION("Renesas TPU PWM Driver");
468 MODULE_ALIAS("platform:renesas-tpu-pwm");