Lines Matching full:definitions

519 /* Bit definitions for the MAJ_REL register */
524 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
534 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
544 /* Bit definitions for the GPIO0_TO_7_OUT register */
554 /* Bit definitions for the GPIO8_TO_15_OUT register */
564 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
569 /* Bit definitions for the DPLL_MODE register */
576 /* Bit definitions for the GPIO_CFG_GBL register */
580 /* Bit definitions for the GPIO_DCO_INC_DEC register */
584 /* Bit definitions for the GPIO_OUT_CTRL_0 register */
594 /* Bit definitions for the GPIO_OUT_CTRL_1 register */
604 /* Bit definitions for the GPIO_TOD_TRIG register */
610 /* Bit definitions for the GPIO_DPLL_INDICATOR register */
614 /* Bit definitions for the GPIO_LOS_INDICATOR register */
620 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
630 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
640 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
650 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
654 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
660 /* Bit definitions for the GPIO_CTRL register */
668 /* Bit definitions for the OUT_CTRL_1 register */
677 /* Bit definitions for the TOD_CFG register */
682 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
688 /* Bit definitions for the TOD_WRITE_CMD register */
695 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
701 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
706 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */