43 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)  in sunxi_pinctrl_find_group_by_name()  argument
47 	for (i = 0; i < pctl->ngroups; i++) {  in sunxi_pinctrl_find_group_by_name()
48 		struct sunxi_pinctrl_group *grp = pctl->groups + i;  in sunxi_pinctrl_find_group_by_name()
58 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_find_function_by_name()  argument
61 	struct sunxi_pinctrl_function *func = pctl->functions;  in sunxi_pinctrl_find_function_by_name()
64 	for (i = 0; i < pctl->nfunctions; i++) {  in sunxi_pinctrl_find_function_by_name()
76 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_desc_find_function_by_name()  argument
82 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_name()
83 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_name()
91 					func->variant & pctl->variant))  in sunxi_pinctrl_desc_find_function_by_name()
103 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_desc_find_function_by_pin()  argument
109 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_pin()
110 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_pin()
129 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_groups_count()  local
131 	return pctl->ngroups;  in sunxi_pctrl_get_groups_count()
137 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_group_name()  local
139 	return pctl->groups[group].name;  in sunxi_pctrl_get_group_name()
147 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_group_pins()  local
149 	*pins = (unsigned *)&pctl->groups[group].pin;  in sunxi_pctrl_get_group_pins()
325 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_dt_node_to_map()  local
337 		dev_err(pctl->dev, "missing function property in node %pOFn\n",  in sunxi_pctrl_dt_node_to_map()
344 		dev_err(pctl->dev, "missing pins property in node %pOFn\n",  in sunxi_pctrl_dt_node_to_map()
369 			sunxi_pinctrl_find_group_by_name(pctl, group);  in sunxi_pctrl_dt_node_to_map()
372 			dev_err(pctl->dev, "unknown pin %s", group);  in sunxi_pctrl_dt_node_to_map()
376 		if (!sunxi_pinctrl_desc_find_function_by_name(pctl,  in sunxi_pctrl_dt_node_to_map()
379 			dev_err(pctl->dev, "unsupported function %s on pin %s",  in sunxi_pctrl_dt_node_to_map()
475 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_get()  local
481 	pin -= pctl->desc->pin_base;  in sunxi_pconf_get()
487 	val = (readl(pctl->membase + offset) >> shift) & mask;  in sunxi_pconf_get()
527 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_group_get()  local
528 	struct sunxi_pinctrl_group *g = &pctl->groups[group];  in sunxi_pconf_group_get()
537 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_set()  local
586 		raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pconf_set()
587 		reg = readl(pctl->membase + offset);  in sunxi_pconf_set()
589 		writel(reg | val << shift, pctl->membase + offset);  in sunxi_pconf_set()
590 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pconf_set()
599 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_group_set()  local
600 	struct sunxi_pinctrl_group *g = &pctl->groups[group];  in sunxi_pconf_group_set()
614 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_set_io_bias_cfg()  argument
623 	if (!pctl->desc->io_bias_cfg_variant)  in sunxi_pinctrl_set_io_bias_cfg()
634 	switch (pctl->desc->io_bias_cfg_variant) {  in sunxi_pinctrl_set_io_bias_cfg()
651 		pin -= pctl->desc->pin_base;  in sunxi_pinctrl_set_io_bias_cfg()
653 		reg = readl(pctl->membase + sunxi_grp_config_reg(pin));  in sunxi_pinctrl_set_io_bias_cfg()
655 		writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));  in sunxi_pinctrl_set_io_bias_cfg()
660 		raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
661 		reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
663 		writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
664 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
673 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_funcs_cnt()  local
675 	return pctl->nfunctions;  in sunxi_pmx_get_funcs_cnt()
681 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_func_name()  local
683 	return pctl->functions[function].name;  in sunxi_pmx_get_func_name()
691 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_func_groups()  local
693 	*groups = pctl->functions[function].groups;  in sunxi_pmx_get_func_groups()
694 	*num_groups = pctl->functions[function].ngroups;  in sunxi_pmx_get_func_groups()
703 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_set()  local
707 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pmx_set()
709 	pin -= pctl->desc->pin_base;  in sunxi_pmx_set()
710 	val = readl(pctl->membase + sunxi_mux_reg(pin));  in sunxi_pmx_set()
713 		pctl->membase + sunxi_mux_reg(pin));  in sunxi_pmx_set()
715 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pmx_set()
722 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_set_mux()  local
723 	struct sunxi_pinctrl_group *g = pctl->groups + group;  in sunxi_pmx_set_mux()
724 	struct sunxi_pinctrl_function *func = pctl->functions + function;  in sunxi_pmx_set_mux()
726 		sunxi_pinctrl_desc_find_function_by_name(pctl,  in sunxi_pmx_set_mux()
744 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_gpio_set_direction()  local
753 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);  in sunxi_pmx_gpio_set_direction()
764 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_request()  local
766 	unsigned short bank_offset = bank - pctl->desc->pin_base /  in sunxi_pmx_request()
768 	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];  in sunxi_pmx_request()
779 	reg = regulator_get(pctl->dev, supply);  in sunxi_pmx_request()
781 		dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",  in sunxi_pmx_request()
788 		dev_err(pctl->dev,  in sunxi_pmx_request()
793 	sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);  in sunxi_pmx_request()
808 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_free()  local
810 	unsigned short bank_offset = bank - pctl->desc->pin_base /  in sunxi_pmx_free()
812 	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];  in sunxi_pmx_free()
843 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_get()  local
846 	bool set_mux = pctl->desc->irq_read_needs_mux &&  in sunxi_pinctrl_gpio_get()
852 		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);  in sunxi_pinctrl_gpio_get()
854 	val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;  in sunxi_pinctrl_gpio_get()
857 		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);  in sunxi_pinctrl_gpio_get()
865 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_set()  local
871 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_gpio_set()
873 	regval = readl(pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
880 	writel(regval, pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
882 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_gpio_set()
912 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_to_irq()  local
914 	unsigned pinnum = pctl->desc->pin_base + offset;  in sunxi_pinctrl_gpio_to_irq()
920 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");  in sunxi_pinctrl_gpio_to_irq()
929 	return irq_find_mapping(pctl->domain, irqnum);  in sunxi_pinctrl_gpio_to_irq()
934 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_request_resources()  local
938 	func = sunxi_pinctrl_desc_find_function_by_pin(pctl,  in sunxi_pinctrl_irq_request_resources()
939 					pctl->irq_array[d->hwirq], "irq");  in sunxi_pinctrl_irq_request_resources()
943 	ret = gpiochip_lock_as_irq(pctl->chip,  in sunxi_pinctrl_irq_request_resources()
944 			pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_request_resources()
946 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",  in sunxi_pinctrl_irq_request_resources()
952 	sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);  in sunxi_pinctrl_irq_request_resources()
959 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_release_resources()  local
961 	gpiochip_unlock_as_irq(pctl->chip,  in sunxi_pinctrl_irq_release_resources()
962 			      pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_release_resources()
967 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_set_type()  local
968 	u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_set_type()
994 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_set_type()
1003 	regval = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
1005 	writel(regval | (mode << index), pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
1007 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_set_type()
1014 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_ack()  local
1015 	u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_ack()
1019 	writel(1 << status_idx, pctl->membase + status_reg);  in sunxi_pinctrl_irq_ack()
1024 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_mask()  local
1025 	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_mask()
1030 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_mask()
1033 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
1034 	writel(val & ~(1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
1036 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_mask()
1041 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_unmask()  local
1042 	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_unmask()
1047 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_unmask()
1050 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
1051 	writel(val | (1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
1053 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_unmask()
1064 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_set_wake()  local
1067 	return irq_set_irq_wake(pctl->irq[bank], on);  in sunxi_pinctrl_irq_set_wake()
1107 	struct sunxi_pinctrl *pctl = d->host_data;  in sunxi_pinctrl_irq_of_xlate()  local
1115 	pin = pctl->desc->pin_base + base + intspec[1];  in sunxi_pinctrl_irq_of_xlate()
1117 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");  in sunxi_pinctrl_irq_of_xlate()
1135 	struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);  in sunxi_pinctrl_irq_handler()  local
1138 	for (bank = 0; bank < pctl->desc->irq_banks; bank++)  in sunxi_pinctrl_irq_handler()
1139 		if (irq == pctl->irq[bank])  in sunxi_pinctrl_irq_handler()
1142 	if (bank == pctl->desc->irq_banks)  in sunxi_pinctrl_irq_handler()
1145 	reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);  in sunxi_pinctrl_irq_handler()
1146 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_handler()
1153 			int pin_irq = irq_find_mapping(pctl->domain,  in sunxi_pinctrl_irq_handler()
1161 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_add_function()  argument
1164 	struct sunxi_pinctrl_function *func = pctl->functions;  in sunxi_pinctrl_add_function()
1178 	pctl->nfunctions++;  in sunxi_pinctrl_add_function()
1185 	struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);  in sunxi_pinctrl_build_state()  local
1200 	pctl->groups = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_build_state()
1201 				    pctl->desc->npins, sizeof(*pctl->groups),  in sunxi_pinctrl_build_state()
1203 	if (!pctl->groups)  in sunxi_pinctrl_build_state()
1206 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1207 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1208 		struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;  in sunxi_pinctrl_build_state()
1210 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1217 		pctl->ngroups++;  in sunxi_pinctrl_build_state()
1224 	pctl->functions = kcalloc(pctl->ngroups,  in sunxi_pinctrl_build_state()
1225 				  sizeof(*pctl->functions),  in sunxi_pinctrl_build_state()
1227 	if (!pctl->functions)  in sunxi_pinctrl_build_state()
1231 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1232 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1235 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1239 			if (func->variant && !(pctl->variant & func->variant))  in sunxi_pinctrl_build_state()
1245 				pctl->irq_array[irqnum] = pin->pin.number;  in sunxi_pinctrl_build_state()
1248 			sunxi_pinctrl_add_function(pctl, func->name);  in sunxi_pinctrl_build_state()
1253 	ptr = krealloc(pctl->functions,  in sunxi_pinctrl_build_state()
1254 		       pctl->nfunctions * sizeof(*pctl->functions),  in sunxi_pinctrl_build_state()
1257 		kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1258 		pctl->functions = NULL;  in sunxi_pinctrl_build_state()
1261 	pctl->functions = ptr;  in sunxi_pinctrl_build_state()
1263 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1264 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1267 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1274 			if (func->variant && !(pctl->variant & func->variant))  in sunxi_pinctrl_build_state()
1277 			func_item = sunxi_pinctrl_find_function_by_name(pctl,  in sunxi_pinctrl_build_state()
1280 				kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1291 					kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1329 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_setup_debounce()  argument
1346 	losc = devm_clk_get(pctl->dev, "losc");  in sunxi_pinctrl_setup_debounce()
1350 	hosc = devm_clk_get(pctl->dev, "hosc");  in sunxi_pinctrl_setup_debounce()
1354 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_setup_debounce()
1384 		       pctl->membase +  in sunxi_pinctrl_setup_debounce()
1385 		       sunxi_irq_debounce_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_setup_debounce()
1398 	struct sunxi_pinctrl *pctl;  in sunxi_pinctrl_init_with_variant()  local
1403 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);  in sunxi_pinctrl_init_with_variant()
1404 	if (!pctl)  in sunxi_pinctrl_init_with_variant()
1406 	platform_set_drvdata(pdev, pctl);  in sunxi_pinctrl_init_with_variant()
1408 	raw_spin_lock_init(&pctl->lock);  in sunxi_pinctrl_init_with_variant()
1410 	pctl->membase = devm_platform_ioremap_resource(pdev, 0);  in sunxi_pinctrl_init_with_variant()
1411 	if (IS_ERR(pctl->membase))  in sunxi_pinctrl_init_with_variant()
1412 		return PTR_ERR(pctl->membase);  in sunxi_pinctrl_init_with_variant()
1414 	pctl->dev = &pdev->dev;  in sunxi_pinctrl_init_with_variant()
1415 	pctl->desc = desc;  in sunxi_pinctrl_init_with_variant()
1416 	pctl->variant = variant;  in sunxi_pinctrl_init_with_variant()
1418 	pctl->irq_array = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_init_with_variant()
1419 				       IRQ_PER_BANK * pctl->desc->irq_banks,  in sunxi_pinctrl_init_with_variant()
1420 				       sizeof(*pctl->irq_array),  in sunxi_pinctrl_init_with_variant()
1422 	if (!pctl->irq_array)  in sunxi_pinctrl_init_with_variant()
1432 			    pctl->desc->npins, sizeof(*pins),  in sunxi_pinctrl_init_with_variant()
1437 	for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_init_with_variant()
1438 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_init_with_variant()
1440 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_init_with_variant()
1455 	pctrl_desc->npins = pctl->ngroups;  in sunxi_pinctrl_init_with_variant()
1469 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);  in sunxi_pinctrl_init_with_variant()
1470 	if (IS_ERR(pctl->pctl_dev)) {  in sunxi_pinctrl_init_with_variant()
1472 		return PTR_ERR(pctl->pctl_dev);  in sunxi_pinctrl_init_with_variant()
1475 	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);  in sunxi_pinctrl_init_with_variant()
1476 	if (!pctl->chip)  in sunxi_pinctrl_init_with_variant()
1479 	last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;  in sunxi_pinctrl_init_with_variant()
1480 	pctl->chip->owner = THIS_MODULE;  in sunxi_pinctrl_init_with_variant()
1481 	pctl->chip->request = gpiochip_generic_request;  in sunxi_pinctrl_init_with_variant()
1482 	pctl->chip->free = gpiochip_generic_free;  in sunxi_pinctrl_init_with_variant()
1483 	pctl->chip->set_config = gpiochip_generic_config;  in sunxi_pinctrl_init_with_variant()
1484 	pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;  in sunxi_pinctrl_init_with_variant()
1485 	pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;  in sunxi_pinctrl_init_with_variant()
1486 	pctl->chip->get = sunxi_pinctrl_gpio_get;  in sunxi_pinctrl_init_with_variant()
1487 	pctl->chip->set = sunxi_pinctrl_gpio_set;  in sunxi_pinctrl_init_with_variant()
1488 	pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;  in sunxi_pinctrl_init_with_variant()
1489 	pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;  in sunxi_pinctrl_init_with_variant()
1490 	pctl->chip->of_gpio_n_cells = 3;  in sunxi_pinctrl_init_with_variant()
1491 	pctl->chip->can_sleep = false;  in sunxi_pinctrl_init_with_variant()
1492 	pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -  in sunxi_pinctrl_init_with_variant()
1493 			    pctl->desc->pin_base;  in sunxi_pinctrl_init_with_variant()
1494 	pctl->chip->label = dev_name(&pdev->dev);  in sunxi_pinctrl_init_with_variant()
1495 	pctl->chip->parent = &pdev->dev;  in sunxi_pinctrl_init_with_variant()
1496 	pctl->chip->base = pctl->desc->pin_base;  in sunxi_pinctrl_init_with_variant()
1498 	ret = gpiochip_add_data(pctl->chip, pctl);  in sunxi_pinctrl_init_with_variant()
1502 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_init_with_variant()
1503 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_init_with_variant()
1505 		ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),  in sunxi_pinctrl_init_with_variant()
1506 					     pin->pin.number - pctl->desc->pin_base,  in sunxi_pinctrl_init_with_variant()
1523 	pctl->irq = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_init_with_variant()
1524 				 pctl->desc->irq_banks,  in sunxi_pinctrl_init_with_variant()
1525 				 sizeof(*pctl->irq),  in sunxi_pinctrl_init_with_variant()
1527 	if (!pctl->irq) {  in sunxi_pinctrl_init_with_variant()
1532 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init_with_variant()
1533 		pctl->irq[i] = platform_get_irq(pdev, i);  in sunxi_pinctrl_init_with_variant()
1534 		if (pctl->irq[i] < 0) {  in sunxi_pinctrl_init_with_variant()
1535 			ret = pctl->irq[i];  in sunxi_pinctrl_init_with_variant()
1540 	pctl->domain = irq_domain_add_linear(node,  in sunxi_pinctrl_init_with_variant()
1541 					     pctl->desc->irq_banks * IRQ_PER_BANK,  in sunxi_pinctrl_init_with_variant()
1543 					     pctl);  in sunxi_pinctrl_init_with_variant()
1544 	if (!pctl->domain) {  in sunxi_pinctrl_init_with_variant()
1550 	for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {  in sunxi_pinctrl_init_with_variant()
1551 		int irqno = irq_create_mapping(pctl->domain, i);  in sunxi_pinctrl_init_with_variant()
1555 		irq_set_chip_data(irqno, pctl);  in sunxi_pinctrl_init_with_variant()
1558 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init_with_variant()
1560 		writel(0, pctl->membase +  in sunxi_pinctrl_init_with_variant()
1561 			  sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_init_with_variant()
1563 		       pctl->membase +  in sunxi_pinctrl_init_with_variant()
1564 		       sunxi_irq_status_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_init_with_variant()
1566 		irq_set_chained_handler_and_data(pctl->irq[i],  in sunxi_pinctrl_init_with_variant()
1568 						 pctl);  in sunxi_pinctrl_init_with_variant()
1571 	sunxi_pinctrl_setup_debounce(pctl, node);  in sunxi_pinctrl_init_with_variant()
1580 	gpiochip_remove(pctl->chip);  in sunxi_pinctrl_init_with_variant()