1 // SPDX-License-Identifier: GPL-2.0
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
11 #include <linux/hwspinlock.h>
23 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
112 	struct hwspinlock *hwlock;
145 		return function - 1;  in stm32_gpio_get_alt()
156 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);  in stm32_gpio_backup_value()
157 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;  in stm32_gpio_backup_value()
163 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |  in stm32_gpio_backup_mode()
165 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;  in stm32_gpio_backup_mode()
166 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;  in stm32_gpio_backup_mode()
172 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);  in stm32_gpio_backup_driving()
173 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;  in stm32_gpio_backup_driving()
179 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;  in stm32_gpio_backup_speed()
180 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;  in stm32_gpio_backup_speed()
186 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;  in stm32_gpio_backup_bias()
187 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;  in stm32_gpio_backup_bias()
200 	clk_enable(bank->clk);  in __stm32_gpio_set()
202 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);  in __stm32_gpio_set()
204 	clk_disable(bank->clk);  in __stm32_gpio_set()
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_request()
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);  in stm32_gpio_request()
214 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);  in stm32_gpio_request()
216 		dev_err(pctl->dev, "pin %d not in range.\n", pin);  in stm32_gpio_request()
217 		return -EINVAL;  in stm32_gpio_request()
220 	return pinctrl_gpio_request(chip->base + offset);  in stm32_gpio_request()
225 	pinctrl_gpio_free(chip->base + offset);  in stm32_gpio_free()
233 	clk_enable(bank->clk);  in stm32_gpio_get()
235 	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));  in stm32_gpio_get()
237 	clk_disable(bank->clk);  in stm32_gpio_get()
251 	return pinctrl_gpio_direction_input(chip->base + offset);  in stm32_gpio_direction_input()
260 	pinctrl_gpio_direction_output(chip->base + offset);  in stm32_gpio_direction_output()
271 	fwspec.fwnode = bank->fwnode;  in stm32_gpio_to_irq()
292 		ret = -EINVAL;  in stm32_gpio_get_direction()
311 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_irq_trigger()
315 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);  in stm32_gpio_irq_trigger()
316 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||  in stm32_gpio_irq_trigger()
317 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))  in stm32_gpio_irq_trigger()
329 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_set_type()
345 		return -EINVAL;  in stm32_gpio_set_type()
348 	bank->irq_type[d->hwirq] = type;  in stm32_gpio_set_type()
355 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_request_resources()
356 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_irq_request_resources()
359 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
363 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
365 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",  in stm32_gpio_irq_request_resources()
366 			irq_data->hwirq);  in stm32_gpio_irq_request_resources()
375 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_release_resources()
377 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_release_resources()
403 	if ((fwspec->param_count != 2) ||  in stm32_gpio_domain_translate()
404 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))  in stm32_gpio_domain_translate()
405 		return -EINVAL;  in stm32_gpio_domain_translate()
407 	*hwirq = fwspec->param[0];  in stm32_gpio_domain_translate()
408 	*type = fwspec->param[1];  in stm32_gpio_domain_translate()
415 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_activate()
416 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_activate()
424 	spin_lock_irqsave(&pctl->irqmux_lock, flags);  in stm32_gpio_domain_activate()
426 	if (pctl->hwlock) {  in stm32_gpio_domain_activate()
427 		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,  in stm32_gpio_domain_activate()
430 			dev_err(pctl->dev, "Can't get hwspinlock\n");  in stm32_gpio_domain_activate()
435 	if (pctl->irqmux_map & BIT(irq_data->hwirq)) {  in stm32_gpio_domain_activate()
436 		dev_err(pctl->dev, "irq line %ld already requested.\n",  in stm32_gpio_domain_activate()
437 			irq_data->hwirq);  in stm32_gpio_domain_activate()
438 		ret = -EBUSY;  in stm32_gpio_domain_activate()
439 		if (pctl->hwlock)  in stm32_gpio_domain_activate()
440 			hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_gpio_domain_activate()
443 		pctl->irqmux_map |= BIT(irq_data->hwirq);  in stm32_gpio_domain_activate()
446 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);  in stm32_gpio_domain_activate()
448 	if (pctl->hwlock)  in stm32_gpio_domain_activate()
449 		hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_gpio_domain_activate()
452 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);  in stm32_gpio_domain_activate()
459 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_deactivate()
460 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_deactivate()
463 	spin_lock_irqsave(&pctl->irqmux_lock, flags);  in stm32_gpio_domain_deactivate()
464 	pctl->irqmux_map &= ~BIT(irq_data->hwirq);  in stm32_gpio_domain_deactivate()
465 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);  in stm32_gpio_domain_deactivate()
472 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_alloc()
477 	hwirq = fwspec->param[0];  in stm32_gpio_domain_alloc()
478 	parent_fwspec.fwnode = d->parent->fwnode;  in stm32_gpio_domain_alloc()
480 	parent_fwspec.param[0] = fwspec->param[0];  in stm32_gpio_domain_alloc()
481 	parent_fwspec.param[1] = fwspec->param[1];  in stm32_gpio_domain_alloc()
503 	for (i = 0; i < pctl->ngroups; i++) {  in stm32_pctrl_find_group_by_pin()
504 		struct stm32_pinctrl_group *grp = pctl->groups + i;  in stm32_pctrl_find_group_by_pin()
506 		if (grp->pin == pin)  in stm32_pctrl_find_group_by_pin()
518 	for (i = 0; i < pctl->npins; i++) {  in stm32_pctrl_is_function_valid()
519 		const struct stm32_desc_pin *pin = pctl->pins + i;  in stm32_pctrl_is_function_valid()
520 		const struct stm32_desc_function *func = pin->functions;  in stm32_pctrl_is_function_valid()
522 		if (pin->pin.number != pin_num)  in stm32_pctrl_is_function_valid()
525 		while (func && func->name) {  in stm32_pctrl_is_function_valid()
526 			if (func->num == fnum)  in stm32_pctrl_is_function_valid()
543 		return -ENOSPC;  in stm32_pctrl_dt_node_to_map_func()
546 	(*map)[*num_maps].data.mux.group = grp->name;  in stm32_pctrl_dt_node_to_map_func()
549 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",  in stm32_pctrl_dt_node_to_map_func()
551 		return -EINVAL;  in stm32_pctrl_dt_node_to_map_func()
580 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",  in stm32_pctrl_dt_subnode_to_map()
582 		return -EINVAL;  in stm32_pctrl_dt_subnode_to_map()
593 	num_pins = pins->length / sizeof(u32);  in stm32_pctrl_dt_subnode_to_map()
602 		err = -EINVAL;  in stm32_pctrl_dt_subnode_to_map()
623 			dev_err(pctl->dev, "invalid function.\n");  in stm32_pctrl_dt_subnode_to_map()
624 			err = -EINVAL;  in stm32_pctrl_dt_subnode_to_map()
630 			dev_err(pctl->dev, "unable to match pin %d to group\n",  in stm32_pctrl_dt_subnode_to_map()
632 			err = -EINVAL;  in stm32_pctrl_dt_subnode_to_map()
643 					reserved_maps, num_maps, grp->name,  in stm32_pctrl_dt_subnode_to_map()
685 	return pctl->ngroups;  in stm32_pctrl_get_groups_count()
693 	return pctl->groups[group].name;  in stm32_pctrl_get_group_name()
703 	*pins = (unsigned *)&pctl->groups[group].pin;  in stm32_pctrl_get_group_pins()
738 	*groups = pctl->grp_names;  in stm32_pmx_get_func_groups()
739 	*num_groups = pctl->ngroups;  in stm32_pmx_get_func_groups()
747 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pmx_set_mode()
754 	clk_enable(bank->clk);  in stm32_pmx_set_mode()
755 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_set_mode()
757 	if (pctl->hwlock) {  in stm32_pmx_set_mode()
758 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,  in stm32_pmx_set_mode()
761 			dev_err(pctl->dev, "Can't get hwspinlock\n");  in stm32_pmx_set_mode()
766 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_set_mode()
769 	writel_relaxed(val, bank->base + alt_offset);  in stm32_pmx_set_mode()
771 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
774 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
776 	if (pctl->hwlock)  in stm32_pmx_set_mode()
777 		hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_pmx_set_mode()
782 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_set_mode()
783 	clk_disable(bank->clk);  in stm32_pmx_set_mode()
796 	clk_enable(bank->clk);  in stm32_pmx_get_mode()
797 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_get_mode()
799 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_get_mode()
803 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_get_mode()
807 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_get_mode()
808 	clk_disable(bank->clk);  in stm32_pmx_get_mode()
817 	struct stm32_pinctrl_group *g = pctl->groups + group;  in stm32_pmx_set_mux()
823 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);  in stm32_pmx_set_mux()
825 		dev_err(pctl->dev, "invalid function %d on group %d .\n",  in stm32_pmx_set_mux()
827 		return -EINVAL;  in stm32_pmx_set_mux()
830 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);  in stm32_pmx_set_mux()
832 		dev_err(pctl->dev, "No gpio range defined.\n");  in stm32_pmx_set_mux()
833 		return -EINVAL;  in stm32_pmx_set_mux()
836 	bank = gpiochip_get_data(range->gc);  in stm32_pmx_set_mux()
837 	pin = stm32_gpio_pin(g->pin);  in stm32_pmx_set_mux()
849 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);  in stm32_pmx_gpio_set_direction()
869 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_driving()
874 	clk_enable(bank->clk);  in stm32_pconf_set_driving()
875 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_driving()
877 	if (pctl->hwlock) {  in stm32_pconf_set_driving()
878 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,  in stm32_pconf_set_driving()
881 			dev_err(pctl->dev, "Can't get hwspinlock\n");  in stm32_pconf_set_driving()
886 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
889 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
891 	if (pctl->hwlock)  in stm32_pconf_set_driving()
892 		hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_pconf_set_driving()
897 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_driving()
898 	clk_disable(bank->clk);  in stm32_pconf_set_driving()
909 	clk_enable(bank->clk);  in stm32_pconf_get_driving()
910 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_driving()
912 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_get_driving()
915 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_driving()
916 	clk_disable(bank->clk);  in stm32_pconf_get_driving()
924 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_speed()
929 	clk_enable(bank->clk);  in stm32_pconf_set_speed()
930 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_speed()
932 	if (pctl->hwlock) {  in stm32_pconf_set_speed()
933 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,  in stm32_pconf_set_speed()
936 			dev_err(pctl->dev, "Can't get hwspinlock\n");  in stm32_pconf_set_speed()
941 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
944 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
946 	if (pctl->hwlock)  in stm32_pconf_set_speed()
947 		hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_pconf_set_speed()
952 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_speed()
953 	clk_disable(bank->clk);  in stm32_pconf_set_speed()
964 	clk_enable(bank->clk);  in stm32_pconf_get_speed()
965 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_speed()
967 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_get_speed()
970 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_speed()
971 	clk_disable(bank->clk);  in stm32_pconf_get_speed()
979 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_bias()
984 	clk_enable(bank->clk);  in stm32_pconf_set_bias()
985 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_bias()
987 	if (pctl->hwlock) {  in stm32_pconf_set_bias()
988 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,  in stm32_pconf_set_bias()
991 			dev_err(pctl->dev, "Can't get hwspinlock\n");  in stm32_pconf_set_bias()
996 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
999 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1001 	if (pctl->hwlock)  in stm32_pconf_set_bias()
1002 		hwspin_unlock_in_atomic(pctl->hwlock);  in stm32_pconf_set_bias()
1007 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_bias()
1008 	clk_disable(bank->clk);  in stm32_pconf_set_bias()
1019 	clk_enable(bank->clk);  in stm32_pconf_get_bias()
1020 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_bias()
1022 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_get_bias()
1025 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_bias()
1026 	clk_disable(bank->clk);  in stm32_pconf_get_bias()
1037 	clk_enable(bank->clk);  in stm32_pconf_get()
1038 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get()
1041 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &  in stm32_pconf_get()
1044 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &  in stm32_pconf_get()
1047 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get()
1048 	clk_disable(bank->clk);  in stm32_pconf_get()
1064 		dev_err(pctl->dev, "No gpio range defined.\n");  in stm32_pconf_parse_conf()
1065 		return -EINVAL;  in stm32_pconf_parse_conf()
1068 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_parse_conf()
1095 		ret = -ENOTSUPP;  in stm32_pconf_parse_conf()
1107 	*config = pctl->groups[group].config;  in stm32_pconf_group_get()
1116 	struct stm32_pinctrl_group *g = &pctl->groups[group];  in stm32_pconf_group_set()
1120 		mutex_lock(&pctldev->mutex);  in stm32_pconf_group_set()
1121 		ret = stm32_pconf_parse_conf(pctldev, g->pin,  in stm32_pconf_group_set()
1124 		mutex_unlock(&pctldev->mutex);  in stm32_pconf_group_set()
1128 		g->config = configs[i];  in stm32_pconf_group_set()
1170 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_dbg_show()
1182 		seq_printf(s, "- %s - %s",  in stm32_pconf_dbg_show()
1192 		seq_printf(s, "- %s - %s - %s - %s %s",  in stm32_pconf_dbg_show()
1203 		seq_printf(s, "%d - %s - %s - %s %s", alt,  in stm32_pconf_dbg_show()
1225 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];  in stm32_gpiolib_register_bank()
1227 	struct pinctrl_gpio_range *range = &bank->range;  in stm32_gpiolib_register_bank()
1229 	struct device *dev = pctl->dev;  in stm32_gpiolib_register_bank()
1234 	if (!IS_ERR(bank->rstc))  in stm32_gpiolib_register_bank()
1235 		reset_control_deassert(bank->rstc);  in stm32_gpiolib_register_bank()
1238 		return -ENODEV;  in stm32_gpiolib_register_bank()
1240 	bank->base = devm_ioremap_resource(dev, &res);  in stm32_gpiolib_register_bank()
1241 	if (IS_ERR(bank->base))  in stm32_gpiolib_register_bank()
1242 		return PTR_ERR(bank->base);  in stm32_gpiolib_register_bank()
1244 	err = clk_prepare(bank->clk);  in stm32_gpiolib_register_bank()
1250 	bank->gpio_chip = stm32_gpio_template;  in stm32_gpiolib_register_bank()
1252 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1254 	if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {  in stm32_gpiolib_register_bank()
1256 		bank->gpio_chip.base = args.args[1];  in stm32_gpiolib_register_bank()
1258 		bank_nr = pctl->nbanks;  in stm32_gpiolib_register_bank()
1259 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1260 		range->name = bank->gpio_chip.label;  in stm32_gpiolib_register_bank()
1261 		range->id = bank_nr;  in stm32_gpiolib_register_bank()
1262 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1263 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1264 		range->npins = npins;  in stm32_gpiolib_register_bank()
1265 		range->gc = &bank->gpio_chip;  in stm32_gpiolib_register_bank()
1266 		pinctrl_add_gpio_range(pctl->pctl_dev,  in stm32_gpiolib_register_bank()
1267 				       &pctl->banks[bank_nr].range);  in stm32_gpiolib_register_bank()
1270 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))  in stm32_gpiolib_register_bank()
1273 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1275 	bank->gpio_chip.ngpio = npins;  in stm32_gpiolib_register_bank()
1276 	bank->gpio_chip.of_node = np;  in stm32_gpiolib_register_bank()
1277 	bank->gpio_chip.parent = dev;  in stm32_gpiolib_register_bank()
1278 	bank->bank_nr = bank_nr;  in stm32_gpiolib_register_bank()
1279 	bank->bank_ioport_nr = bank_ioport_nr;  in stm32_gpiolib_register_bank()
1280 	spin_lock_init(&bank->lock);  in stm32_gpiolib_register_bank()
1283 	bank->fwnode = of_node_to_fwnode(np);  in stm32_gpiolib_register_bank()
1285 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,  in stm32_gpiolib_register_bank()
1286 					STM32_GPIO_IRQ_LINE, bank->fwnode,  in stm32_gpiolib_register_bank()
1289 	if (!bank->domain)  in stm32_gpiolib_register_bank()
1290 		return -ENODEV;  in stm32_gpiolib_register_bank()
1292 	err = gpiochip_add_data(&bank->gpio_chip, bank);  in stm32_gpiolib_register_bank()
1298 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1307 	if (!of_find_property(np, "interrupt-parent", NULL))  in stm32_pctrl_get_irq_domain()
1312 		return ERR_PTR(-ENXIO);  in stm32_pctrl_get_irq_domain()
1317 		return ERR_PTR(-EPROBE_DEFER);  in stm32_pctrl_get_irq_domain()
1325 	struct device_node *np = pdev->dev.of_node;  in stm32_pctrl_dt_setup_irq()
1326 	struct device *dev = &pdev->dev;  in stm32_pctrl_dt_setup_irq()
1331 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");  in stm32_pctrl_dt_setup_irq()
1332 	if (IS_ERR(pctl->regmap))  in stm32_pctrl_dt_setup_irq()
1333 		return PTR_ERR(pctl->regmap);  in stm32_pctrl_dt_setup_irq()
1335 	rm = pctl->regmap;  in stm32_pctrl_dt_setup_irq()
1352 		mux.msb = mux.lsb + mask_width - 1;  in stm32_pctrl_dt_setup_irq()
1357 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);  in stm32_pctrl_dt_setup_irq()
1358 		if (IS_ERR(pctl->irqmux[i]))  in stm32_pctrl_dt_setup_irq()
1359 			return PTR_ERR(pctl->irqmux[i]);  in stm32_pctrl_dt_setup_irq()
1370 	pctl->ngroups = pctl->npins;  in stm32_pctrl_build_state()
1373 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,  in stm32_pctrl_build_state()
1374 				    sizeof(*pctl->groups), GFP_KERNEL);  in stm32_pctrl_build_state()
1375 	if (!pctl->groups)  in stm32_pctrl_build_state()
1376 		return -ENOMEM;  in stm32_pctrl_build_state()
1379 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,  in stm32_pctrl_build_state()
1380 				       sizeof(*pctl->grp_names), GFP_KERNEL);  in stm32_pctrl_build_state()
1381 	if (!pctl->grp_names)  in stm32_pctrl_build_state()
1382 		return -ENOMEM;  in stm32_pctrl_build_state()
1384 	for (i = 0; i < pctl->npins; i++) {  in stm32_pctrl_build_state()
1385 		const struct stm32_desc_pin *pin = pctl->pins + i;  in stm32_pctrl_build_state()
1386 		struct stm32_pinctrl_group *group = pctl->groups + i;  in stm32_pctrl_build_state()
1388 		group->name = pin->pin.name;  in stm32_pctrl_build_state()
1389 		group->pin = pin->pin.number;  in stm32_pctrl_build_state()
1390 		pctl->grp_names[i] = pin->pin.name;  in stm32_pctrl_build_state()
1402 	for (i = 0; i < pctl->match_data->npins; i++) {  in stm32_pctrl_create_pins_tab()
1403 		p = pctl->match_data->pins + i;  in stm32_pctrl_create_pins_tab()
1404 		if (pctl->pkg && !(pctl->pkg & p->pkg))  in stm32_pctrl_create_pins_tab()
1406 		pins->pin = p->pin;  in stm32_pctrl_create_pins_tab()
1407 		pins->functions = p->functions;  in stm32_pctrl_create_pins_tab()
1412 	pctl->npins = nb_pins_available;  in stm32_pctrl_create_pins_tab()
1420 	if (of_property_read_u32(np, "st,package", &pctl->pkg)) {  in stm32_pctl_get_package()
1421 		pctl->pkg = 0;  in stm32_pctl_get_package()
1422 		dev_warn(pctl->dev, "No package detected, use default one\n");  in stm32_pctl_get_package()
1424 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);  in stm32_pctl_get_package()
1430 	struct device_node *np = pdev->dev.of_node;  in stm32_pctl_probe()
1433 	struct device *dev = &pdev->dev;  in stm32_pctl_probe()
1439 		return -EINVAL;  in stm32_pctl_probe()
1441 	match = of_match_device(dev->driver->of_match_table, dev);  in stm32_pctl_probe()
1442 	if (!match || !match->data)  in stm32_pctl_probe()
1443 		return -EINVAL;  in stm32_pctl_probe()
1445 	if (!of_find_property(np, "pins-are-numbered", NULL)) {  in stm32_pctl_probe()
1446 		dev_err(dev, "only support pins-are-numbered format\n");  in stm32_pctl_probe()
1447 		return -EINVAL;  in stm32_pctl_probe()
1452 		return -ENOMEM;  in stm32_pctl_probe()
1457 	pctl->domain = stm32_pctrl_get_irq_domain(np);  in stm32_pctl_probe()
1458 	if (IS_ERR(pctl->domain))  in stm32_pctl_probe()
1459 		return PTR_ERR(pctl->domain);  in stm32_pctl_probe()
1461 	/* hwspinlock is optional */  in stm32_pctl_probe()
1462 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);  in stm32_pctl_probe()
1464 		if (hwlock_id == -EPROBE_DEFER)  in stm32_pctl_probe()
1467 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);  in stm32_pctl_probe()
1470 	spin_lock_init(&pctl->irqmux_lock);  in stm32_pctl_probe()
1472 	pctl->dev = dev;  in stm32_pctl_probe()
1473 	pctl->match_data = match->data;  in stm32_pctl_probe()
1478 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,  in stm32_pctl_probe()
1479 				  sizeof(*pctl->pins), GFP_KERNEL);  in stm32_pctl_probe()
1480 	if (!pctl->pins)  in stm32_pctl_probe()
1481 		return -ENOMEM;  in stm32_pctl_probe()
1483 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);  in stm32_pctl_probe()
1490 		return -EINVAL;  in stm32_pctl_probe()
1493 	if (pctl->domain) {  in stm32_pctl_probe()
1499 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),  in stm32_pctl_probe()
1502 		return -ENOMEM;  in stm32_pctl_probe()
1504 	for (i = 0; i < pctl->npins; i++)  in stm32_pctl_probe()
1505 		pins[i] = pctl->pins[i].pin;  in stm32_pctl_probe()
1507 	pctl->pctl_desc.name = dev_name(&pdev->dev);  in stm32_pctl_probe()
1508 	pctl->pctl_desc.owner = THIS_MODULE;  in stm32_pctl_probe()
1509 	pctl->pctl_desc.pins = pins;  in stm32_pctl_probe()
1510 	pctl->pctl_desc.npins = pctl->npins;  in stm32_pctl_probe()
1511 	pctl->pctl_desc.link_consumers = true;  in stm32_pctl_probe()
1512 	pctl->pctl_desc.confops = &stm32_pconf_ops;  in stm32_pctl_probe()
1513 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;  in stm32_pctl_probe()
1514 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;  in stm32_pctl_probe()
1515 	pctl->dev = &pdev->dev;  in stm32_pctl_probe()
1517 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,  in stm32_pctl_probe()
1520 	if (IS_ERR(pctl->pctl_dev)) {  in stm32_pctl_probe()
1521 		dev_err(&pdev->dev, "Failed pinctrl registration\n");  in stm32_pctl_probe()
1522 		return PTR_ERR(pctl->pctl_dev);  in stm32_pctl_probe()
1526 		if (of_property_read_bool(child, "gpio-controller"))  in stm32_pctl_probe()
1531 		return -EINVAL;  in stm32_pctl_probe()
1533 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),  in stm32_pctl_probe()
1535 	if (!pctl->banks)  in stm32_pctl_probe()
1536 		return -ENOMEM;  in stm32_pctl_probe()
1540 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()
1542 		if (of_property_read_bool(child, "gpio-controller")) {  in stm32_pctl_probe()
1543 			bank->rstc = of_reset_control_get_exclusive(child,  in stm32_pctl_probe()
1545 			if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)  in stm32_pctl_probe()
1546 				return -EPROBE_DEFER;  in stm32_pctl_probe()
1548 			bank->clk = of_clk_get_by_name(child, NULL);  in stm32_pctl_probe()
1549 			if (IS_ERR(bank->clk)) {  in stm32_pctl_probe()
1550 				if (PTR_ERR(bank->clk) != -EPROBE_DEFER)  in stm32_pctl_probe()
1553 						PTR_ERR(bank->clk));  in stm32_pctl_probe()
1554 				return PTR_ERR(bank->clk);  in stm32_pctl_probe()
1561 		if (of_property_read_bool(child, "gpio-controller")) {  in stm32_pctl_probe()
1568 			pctl->nbanks++;  in stm32_pctl_probe()
1572 	dev_info(dev, "Pinctrl STM32 initialized\n");  in stm32_pctl_probe()
1580 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);  in stm32_pinctrl_restore_gpio_regs()
1587 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);  in stm32_pinctrl_restore_gpio_regs()
1591 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);  in stm32_pinctrl_restore_gpio_regs()
1593 	if (!desc || (!pin_is_irq && !desc->gpio_owner))  in stm32_pinctrl_restore_gpio_regs()
1596 	bank = gpiochip_get_data(range->gc);  in stm32_pinctrl_restore_gpio_regs()
1598 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;  in stm32_pinctrl_restore_gpio_regs()
1600 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;  in stm32_pinctrl_restore_gpio_regs()
1608 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);  in stm32_pinctrl_restore_gpio_regs()
1613 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);  in stm32_pinctrl_restore_gpio_regs()
1619 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;  in stm32_pinctrl_restore_gpio_regs()
1625 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;  in stm32_pinctrl_restore_gpio_regs()
1632 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);  in stm32_pinctrl_restore_gpio_regs()
1640 	struct stm32_pinctrl_group *g = pctl->groups;  in stm32_pinctrl_resume()
1643 	for (i = g->pin; i < g->pin + pctl->ngroups; i++)  in stm32_pinctrl_resume()