Lines Matching +full:3 +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0
11 * This includes SoCs which are sub- or super- sets of this particular line,
24 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
47 #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4)) argument
74 /* ----------------------------------------------------------------------------
79 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
87 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
88 * Each struct rza1_bidir_entry describes a port.
96 * rza1_swio_pin - describe a single pin that needs swio flag applied.
100 u16 port: 4; member
106 * rza1_swio_entry - describe a list of pins that needs swio flag applied
114 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
121 /* ----------------------------------------------------------------------------
129 { .pin = 3, .func = 1 },
140 { .pin = 3, .func = 1 },
145 { .pin = 3, .func = 4 },
164 { .pin = 3, .func = 2 },
181 { .pin = 3, .func = 8 },
182 { .pin = 10, .func = 3 },
183 { .pin = 11, .func = 3 },
184 { .pin = 13, .func = 3 },
185 { .pin = 14, .func = 3 },
186 { .pin = 15, .func = 3 },
202 { .pin = 3, .func = 1 },
218 { .pin = 13, .func = 3 },
222 { .pin = 8, .func = 3 },
223 { .pin = 9, .func = 3 },
224 { .pin = 10, .func = 3 },
225 { .pin = 11, .func = 3 },
228 { .pin = 14, .func = 3 },
229 { .pin = 15, .func = 3 },
259 { .port = 2, .pin = 7, .func = 4, .input = 0 },
260 { .port = 2, .pin = 11, .func = 4, .input = 0 },
261 { .port = 3, .pin = 7, .func = 3, .input = 0 },
262 { .port = 3, .pin = 7, .func = 8, .input = 0 },
263 { .port = 4, .pin = 7, .func = 5, .input = 0 },
264 { .port = 4, .pin = 7, .func = 11, .input = 0 },
265 { .port = 4, .pin = 15, .func = 6, .input = 0 },
266 { .port = 5, .pin = 0, .func = 1, .input = 1 },
267 { .port = 5, .pin = 1, .func = 1, .input = 1 },
268 { .port = 5, .pin = 2, .func = 1, .input = 1 },
269 { .port = 5, .pin = 3, .func = 1, .input = 1 },
270 { .port = 5, .pin = 4, .func = 1, .input = 1 },
271 { .port = 5, .pin = 5, .func = 1, .input = 1 },
272 { .port = 5, .pin = 6, .func = 1, .input = 1 },
273 { .port = 5, .pin = 7, .func = 1, .input = 1 },
274 { .port = 7, .pin = 4, .func = 6, .input = 0 },
275 { .port = 7, .pin = 11, .func = 2, .input = 0 },
276 { .port = 8, .pin = 10, .func = 8, .input = 0 },
277 { .port = 10, .pin = 15, .func = 2, .input = 0 },
283 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
302 /* ----------------------------------------------------------------------------
310 { .pin = 3, .func = 1 },
332 { .pin = 3, .func = 2 },
341 { .pin = 3, .func = 1 },
357 { .pin = 3, .func = 2 },
364 { .pin = 3, .func = 1 },
381 { .pin = 3, .func = 2 },
385 { .pin = 2, .func = 3 },
386 { .pin = 3, .func = 3 },
387 { .pin = 5, .func = 3 },
388 { .pin = 6, .func = 3 },
389 { .pin = 7, .func = 3 },
394 { .pin = 0, .func = 3 },
395 { .pin = 1, .func = 3 },
396 { .pin = 3, .func = 3 },
397 { .pin = 4, .func = 3 },
398 { .pin = 5, .func = 3 },
402 { .port = 2, .pin = 8, .func = 2, .input = 0 },
403 { .port = 5, .pin = 6, .func = 3, .input = 0 },
404 { .port = 6, .pin = 6, .func = 3, .input = 0 },
405 { .port = 6, .pin = 10, .func = 3, .input = 0 },
406 { .port = 7, .pin = 10, .func = 2, .input = 0 },
407 { .port = 8, .pin = 2, .func = 3, .input = 0 },
412 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
430 /* ----------------------------------------------------------------------------
434 * struct rza1_mux_conf - describes a pin multiplexing operation
437 * @port: the port where pin sits on
445 u8 port; member
453 * struct rza1_port - describes a pin port
455 * This is mostly useful to lock register writes per-bank and not globally.
458 * @id: port number
460 * @pins: pins sitting on this port
470 * struct rza1_pinctrl - RZ pincontroller device
499 /* ----------------------------------------------------------------------------
502 static inline bool rza1_pinmux_get_bidir(unsigned int port, in rza1_pinmux_get_bidir() argument
507 const struct rza1_bidir_entry *entry = &table[port]; in rza1_pinmux_get_bidir()
511 for (i = 0; i < entry->npins; ++i) { in rza1_pinmux_get_bidir()
512 bidir_pin = &entry->pins[i]; in rza1_pinmux_get_bidir()
513 if (bidir_pin->pin == pin && bidir_pin->func == func) in rza1_pinmux_get_bidir()
520 static inline int rza1_pinmux_get_swio(unsigned int port, in rza1_pinmux_get_swio() argument
529 for (i = 0; i < table->npins; ++i) { in rza1_pinmux_get_swio()
530 swio_pin = &table->pins[i]; in rza1_pinmux_get_swio()
531 if (swio_pin->port == port && swio_pin->pin == pin && in rza1_pinmux_get_swio()
532 swio_pin->func == func) in rza1_pinmux_get_swio()
533 return swio_pin->input; in rza1_pinmux_get_swio()
536 return -ENOENT; in rza1_pinmux_get_swio()
540 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
542 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, in rza1_pinmux_get_flags() argument
547 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; in rza1_pinmux_get_flags()
548 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; in rza1_pinmux_get_flags()
549 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; in rza1_pinmux_get_flags()
553 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries)) in rza1_pinmux_get_flags()
556 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries); in rza1_pinmux_get_flags()
565 /* ----------------------------------------------------------------------------
570 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
573 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, in rza1_set_bit() argument
576 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_set_bit()
587 static inline unsigned int rza1_get_bit(struct rza1_port *port, in rza1_get_bit() argument
590 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); in rza1_get_bit()
596 * rza1_pin_reset() - reset a pin to default initial state
598 * Reset pin state disabling input buffer and bi-directional control,
599 * and configure it as input port.
603 * @port: port where pin sits on
606 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) in rza1_pin_reset() argument
610 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_reset()
611 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0); in rza1_pin_reset()
612 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); in rza1_pin_reset()
614 rza1_set_bit(port, RZA1_PM_REG, pin, 1); in rza1_pin_reset()
615 rza1_set_bit(port, RZA1_PMC_REG, pin, 0); in rza1_pin_reset()
616 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0); in rza1_pin_reset()
617 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_reset()
621 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
623 * When running in output port mode keep PBDC enabled to allow reading the
626 * @port: port where pin sits on
630 static inline void rza1_pin_set_direction(struct rza1_port *port, in rza1_pin_set_direction() argument
635 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set_direction()
637 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1); in rza1_pin_set_direction()
639 rza1_set_bit(port, RZA1_PM_REG, pin, 1); in rza1_pin_set_direction()
640 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); in rza1_pin_set_direction()
642 rza1_set_bit(port, RZA1_PM_REG, pin, 0); in rza1_pin_set_direction()
643 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); in rza1_pin_set_direction()
646 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set_direction()
649 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, in rza1_pin_set() argument
654 spin_lock_irqsave(&port->lock, irqflags); in rza1_pin_set()
655 rza1_set_bit(port, RZA1_P_REG, pin, !!value); in rza1_pin_set()
656 spin_unlock_irqrestore(&port->lock, irqflags); in rza1_pin_set()
659 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) in rza1_pin_get() argument
661 return rza1_get_bit(port, RZA1_PPR_REG, pin); in rza1_pin_get()
665 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
673 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; in rza1_pin_mux_single() local
674 unsigned int pin = mux_conf->pin; in rza1_pin_mux_single()
675 u8 mux_func = mux_conf->mux_func; in rza1_pin_mux_single()
676 u8 mux_flags = mux_conf->mux_flags; in rza1_pin_mux_single()
679 rza1_pin_reset(port, pin); in rza1_pin_mux_single()
682 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, in rza1_pin_mux_single()
690 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); in rza1_pin_mux_single()
695 * Be careful here: the pin mux sub-nodes in device tree in rza1_pin_mux_single()
700 * ---------------------------------------------------- in rza1_pin_mux_single()
703 * PMC PFC PFCE PFCAE (mux_func - 1) in rza1_pin_mux_single()
707 * 1 1 1 0 3 in rza1_pin_mux_single()
712 * ---------------------------------------------------- in rza1_pin_mux_single()
714 mux_func -= 1; in rza1_pin_mux_single()
715 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK); in rza1_pin_mux_single()
716 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK); in rza1_pin_mux_single()
717 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK); in rza1_pin_mux_single()
722 * to I/O direction specified by pin configuration -after- PMC has been in rza1_pin_mux_single()
726 rza1_set_bit(port, RZA1_PM_REG, pin, in rza1_pin_mux_single()
729 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1); in rza1_pin_mux_single()
731 rza1_set_bit(port, RZA1_PMC_REG, pin, 1); in rza1_pin_mux_single()
736 /* ----------------------------------------------------------------------------
741 * rza1_gpio_request() - configure pin in port mode
743 * Configure a pin as gpio (port mode).
752 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_request() local
754 rza1_pin_reset(port, gpio); in rza1_gpio_request()
760 * rza1_gpio_disable_free() - reset a pin
763 * Reset pin to port mode, with input buffer disabled. This overwrites all
764 * port direction settings applied with set_direction
771 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_free() local
773 rza1_pin_reset(port, gpio); in rza1_gpio_free()
778 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_get_direction() local
780 if (rza1_get_bit(port, RZA1_PM_REG, gpio)) in rza1_gpio_get_direction()
789 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_direction_input() local
791 rza1_pin_set_direction(port, gpio, true); in rza1_gpio_direction_input()
800 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_direction_output() local
803 rza1_pin_set(port, gpio, value); in rza1_gpio_direction_output()
804 rza1_pin_set_direction(port, gpio, false); in rza1_gpio_direction_output()
810 * rza1_gpio_get() - read a gpio pin value
813 * Requires bi-directional mode to work when reading the value of a pin
821 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_get() local
823 return rza1_pin_get(port, gpio); in rza1_gpio_get()
829 struct rza1_port *port = gpiochip_get_data(chip); in rza1_gpio_set() local
831 rza1_pin_set(port, gpio, value); in rza1_gpio_set()
843 /* ----------------------------------------------------------------------------
848 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
849 * children sub-nodes
861 return of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
868 return -EINVAL; in rza1_dt_node_pin_count()
871 npins += of_pins->length / sizeof(u32); in rza1_dt_node_pin_count()
878 * rza1_parse_pmx_function() - parse a pin mux sub-node
881 * @np: of pmx sub-node
890 struct pinctrl_dev *pctldev = rza1_pctl->pctl; in rza1_parse_pinmux_node()
902 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); in rza1_parse_pinmux_node()
903 return -ENOENT; in rza1_parse_pinmux_node()
905 npins = of_pins->length / sizeof(u32); in rza1_parse_pinmux_node()
909 * this sub-node in rza1_parse_pinmux_node()
914 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
922 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction in rza1_parse_pinmux_node()
950 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; in rza1_parse_pinmux_node()
951 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); in rza1_parse_pinmux_node()
952 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); in rza1_parse_pinmux_node()
953 mux_conf->mux_func = MUX_FUNC(of_pinconf); in rza1_parse_pinmux_node()
954 mux_conf->mux_flags = pinmux_flags; in rza1_parse_pinmux_node()
956 if (mux_conf->port >= RZA1_NPORTS || in rza1_parse_pinmux_node()
957 mux_conf->pin >= RZA1_PINS_PER_PORT) { in rza1_parse_pinmux_node()
958 dev_err(rza1_pctl->dev, in rza1_parse_pinmux_node()
959 "Wrong port %u pin %u for %s property\n", in rza1_parse_pinmux_node()
960 mux_conf->port, mux_conf->pin, prop_name); in rza1_parse_pinmux_node()
961 return -EINVAL; in rza1_parse_pinmux_node()
964 grpins[i] = mux_conf->id; in rza1_parse_pinmux_node()
971 * rza1_dt_node_to_map() - map a pin mux node to a function/group
996 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); in rza1_dt_node_to_map()
997 return -EINVAL; in rza1_dt_node_to_map()
1003 * except that functions carry an array of per-pin mux configuration in rza1_dt_node_to_map()
1006 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), in rza1_dt_node_to_map()
1008 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), in rza1_dt_node_to_map()
1010 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); in rza1_dt_node_to_map()
1013 return -ENOMEM; in rza1_dt_node_to_map()
1017 * If the node does not contain "pinmux" property (-ENOENT) in rza1_dt_node_to_map()
1018 * that property shall be specified in all its children sub-nodes. in rza1_dt_node_to_map()
1024 if (ret == -ENOENT) in rza1_dt_node_to_map()
1040 grpname = np->name; in rza1_dt_node_to_map()
1043 mutex_lock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1047 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1058 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", in rza1_dt_node_to_map()
1065 ret = -ENOMEM; in rza1_dt_node_to_map()
1069 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in rza1_dt_node_to_map()
1070 (*map)->data.mux.group = np->name; in rza1_dt_node_to_map()
1071 (*map)->data.mux.function = np->name; in rza1_dt_node_to_map()
1073 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1082 mutex_unlock(&rza1_pctl->mutex); in rza1_dt_node_to_map()
1084 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", in rza1_dt_node_to_map()
1104 /* ----------------------------------------------------------------------------
1109 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1126 return -EINVAL; in rza1_set_mux()
1130 return -EINVAL; in rza1_set_mux()
1132 mux_confs = (struct rza1_mux_conf *)func->data; in rza1_set_mux()
1133 for (i = 0; i < grp->num_pins; ++i) { in rza1_set_mux()
1152 /* ----------------------------------------------------------------------------
1162 if (!of_property_read_bool(child, "gpio-controller")) in rza1_count_gpio_chips()
1172 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1174 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1178 * @np: of gpio-controller node
1187 const char *list_name = "gpio-ranges"; in rza1_parse_gpiochip()
1193 ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args); in rza1_parse_gpiochip()
1195 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", in rza1_parse_gpiochip()
1201 * Find out on which port this gpio-chip maps to by inspecting the in rza1_parse_gpiochip()
1202 * second argument of the "gpio-ranges" property. in rza1_parse_gpiochip()
1207 dev_err(rza1_pctl->dev, in rza1_parse_gpiochip()
1209 return -EINVAL; in rza1_parse_gpiochip()
1213 chip->base = -1; in rza1_parse_gpiochip()
1214 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn", in rza1_parse_gpiochip()
1216 if (!chip->label) in rza1_parse_gpiochip()
1217 return -ENOMEM; in rza1_parse_gpiochip()
1219 chip->ngpio = of_args.args[2]; in rza1_parse_gpiochip()
1220 chip->of_node = np; in rza1_parse_gpiochip()
1221 chip->parent = rza1_pctl->dev; in rza1_parse_gpiochip()
1223 range->id = gpioport; in rza1_parse_gpiochip()
1224 range->name = chip->label; in rza1_parse_gpiochip()
1225 range->pin_base = range->base = pinctrl_base; in rza1_parse_gpiochip()
1226 range->npins = of_args.args[2]; in rza1_parse_gpiochip()
1227 range->gc = chip; in rza1_parse_gpiochip()
1229 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, in rza1_parse_gpiochip()
1230 &rza1_pctl->ports[gpioport]); in rza1_parse_gpiochip()
1234 pinctrl_add_gpio_range(rza1_pctl->pctl, range); in rza1_parse_gpiochip()
1236 dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", in rza1_parse_gpiochip()
1237 chip->label, chip->ngpio); in rza1_parse_gpiochip()
1243 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1249 struct device_node *np = rza1_pctl->dev->of_node; in rza1_gpio_register()
1259 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); in rza1_gpio_register()
1263 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1265 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, in rza1_gpio_register()
1268 return -ENOMEM; in rza1_gpio_register()
1272 if (!of_property_read_bool(child, "gpio-controller")) in rza1_gpio_register()
1285 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); in rza1_gpio_register()
1291 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1303 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), in rza1_pinctrl_register()
1305 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), in rza1_pinctrl_register()
1308 return -ENOMEM; in rza1_pinctrl_register()
1310 rza1_pctl->pins = pins; in rza1_pinctrl_register()
1311 rza1_pctl->desc.pins = pins; in rza1_pinctrl_register()
1312 rza1_pctl->desc.npins = RZA1_NPINS; in rza1_pinctrl_register()
1313 rza1_pctl->ports = ports; in rza1_pinctrl_register()
1317 unsigned int port = RZA1_PIN_ID_TO_PORT(i); in rza1_pinctrl_register() local
1320 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, in rza1_pinctrl_register()
1321 "P%u-%u", port, pin); in rza1_pinctrl_register()
1323 return -ENOMEM; in rza1_pinctrl_register()
1328 * they provide per-port lock and logical base address. in rza1_pinctrl_register()
1333 ports[port_id].base = rza1_pctl->base; in rza1_pinctrl_register()
1339 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, in rza1_pinctrl_register()
1340 rza1_pctl, &rza1_pctl->pctl); in rza1_pinctrl_register()
1342 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1347 ret = pinctrl_enable(rza1_pctl->pctl); in rza1_pinctrl_register()
1349 dev_err(rza1_pctl->dev, in rza1_pinctrl_register()
1356 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); in rza1_pinctrl_register()
1368 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); in rza1_pinctrl_probe()
1370 return -ENOMEM; in rza1_pinctrl_probe()
1372 rza1_pctl->dev = &pdev->dev; in rza1_pinctrl_probe()
1374 rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); in rza1_pinctrl_probe()
1375 if (IS_ERR(rza1_pctl->base)) in rza1_pinctrl_probe()
1376 return PTR_ERR(rza1_pctl->base); in rza1_pinctrl_probe()
1378 mutex_init(&rza1_pctl->mutex); in rza1_pinctrl_probe()
1382 rza1_pctl->desc.name = DRIVER_NAME; in rza1_pinctrl_probe()
1383 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; in rza1_pinctrl_probe()
1384 rza1_pctl->desc.pmxops = &rza1_pinmux_ops; in rza1_pinctrl_probe()
1385 rza1_pctl->desc.owner = THIS_MODULE; in rza1_pinctrl_probe()
1386 rza1_pctl->data = of_device_get_match_data(&pdev->dev); in rza1_pinctrl_probe()
1392 dev_info(&pdev->dev, in rza1_pinctrl_probe()
1401 .compatible = "renesas,r7s72100-ports",
1406 .compatible = "renesas,r7s72102-ports",